Abstract: In an embodiment, a transistor device comprises a semiconductor body comprising a plurality of transistor cells comprising a drift region of a first conductivity type, a body region of a second conductivity type forming a first pn junction with the drift region, the second conductivity type opposing the first conductivity type, a source region of the first conductivity type forming a second pn junction with the body region, a columnar field plate trench extending into a major surface of a semiconductor body and comprising a columnar field plate and a gate trench structure extending into the major surface of the semiconductor body and comprising a gate electrode. At least one of the depth and doping level of the body region locally varies within the transistor cell to improve VGSTH homogeneity within the transistor cell.

Abstract: A semiconductor device is described. The semiconductor device includes: a semiconductor substrate; an electrode structure on or in the semiconductor substrate, the electrode structure including an electrode and an insulating material that separates the electrode from the semiconductor substrate; and a strain-inducing material embedded in the electrode. The electrode structure adjoins a region of the semiconductor substrate through which current flows in a first direction during operation of the semiconductor device. The electrode is under either tensile or compressive stress in the first direction. The strain-inducing material either enhances or at least partly counteracts the stress of the electrode in the first direction. Methods of producing the semiconductor device are also described.

Abstract: A semiconductor device includes a transistor cell region, and a first termination region devoid of transistor cells. The transistor cell region includes a gate structure, a plurality of needle-shaped first field plate structures, body regions of a second conductivity type, and source regions of a first conductivity type. The first termination region surrounds the transistor cell region and includes needle-shaped second field plate structures. The needle-shaped first field plate structures are arranged in a first pattern and the needle-shaped second field plate structures are arranged in a second pattern.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a gate structure extending from a first surface into the semiconductor substrate, a plurality of needle-shaped first field plate structures extending from the first surface into the semiconductor substrate, body regions of a second conductivity type, and source regions of a first conductivity type formed between the body regions and the first surface. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The needle-shaped first field plate structures are arranged in a first pattern and the needle-shaped second field plate structures are arranged in a second pattern.

Abstract: A transistor device includes field plate contacts that electrically connect a final metallization layer to field electrodes in underlying trenches, and mesa contacts that electrically connect the final metallization layer to semiconductor mesas confined by the trenches. Each field plate contact is divided into field plate contact segments that are separated from one another. Each mesa contact is divided into mesa contact segments that are separated from one another. In a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts. In a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts.

Abstract: The disclosure relates to a power device, having a channel region, a gate region formed aside the channel region, for controlling a channel formation, a drift region formed vertically below the channel region, a field electrode formed in a field electrode trench extending vertically into the drift region, wherein the field electrode comprises a first and a second field electrode structure, the first field electrode structure capacitively coupling to a first section of the drift region and the second field electrode structure capacitively coupling to a second section of the drift region, arranged vertically above the first section, the first and the second field electrode structure formed with a vertical overlap and adapted to balance a capacitive coupling between the first and the second field electrode structure and between the field electrode and the drift region.

Abstract: In some embodiments, a semiconductor device comprises a semiconductor die comprising a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a second surface opposing the first surface. A first metallization structure is located on the first surface and comprises at least one source pad coupled to the source electrode, at least one drain pad coupled to the drain electrode and at least one gate pad coupled to the gate electrode. A second metallization structure is located on the second surface and comprises a conductive structure and an electrically insulating layer and forms an outermost surface of the semiconductor device. The outermost surface of the second metallization structure is electrically insulated from the semiconductor die by the electrically insulating layer.

Abstract: A transistor device includes field plate contacts that electrically connect overlying contact pads to field electrodes in underlying trenches, and mesa contacts that electrically connect the contact pads to semiconductor mesas confined by the trenches. Each field plate contact is divided into field plate contact segments that are separated from one another. Each mesa contact is divided into mesa contact segments that are separated from one another. In a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts. In a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts.

Abstract: In an embodiment, a semiconductor wafer is provided that includes a plurality of component positions with scribe line regions located at least one of adjacent to and between the component positions. The component positions include an active device structure. An auxiliary structure is positioned in one or more of the scribe line regions. The auxiliary structure is electrically coupled to an auxiliary contact pad which includes tungsten. The auxiliary structure does not interact with or affect the active device structure in the component positions.

Abstract: In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure. The metallization structure includes a first conductive layer above the first surface, a first insulating layer above the first conductive layer, a second conductive layer above the first insulating layer, a second insulating layer above the second conductive layer and a third conductive layer above the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.

Abstract: A semiconductor die is described. The semiconductor die includes a semiconductor body having an active region, a metallization formed on the semiconductor body, and a passivation formed on the metallization. The metallization includes at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. The passivation includes a silicon oxide layer. Corresponding methods of manufacturing and using the semiconductor die are also described.

Abstract: In an embodiment, a semiconductor wafer is provided that includes a plurality of component positions with scribe line regions located at least one of adjacent to and between the component positions. The component positions include an active device structure. An auxiliary structure is positioned in one or more of the scribe line regions. The auxiliary structure is electrically coupled to an auxiliary contact pad which includes tungsten.

Abstract: A power semiconductor die has a semiconductor body coupled to first and second load terminals, and at least one power cell. In a horizontal cross-section of the at least one power cell, a contact has a contact region which horizontally overlaps with a field plate electrode and horizontally protrudes from the field plate trench, and a recess region does not horizontally overlap with the contact region and extends into a horizontal circumference of the field plate trench.

Abstract: In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure located on the first surface. The metallization structure includes a first conductive layer on the first surface, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer and a third conductive layer on the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.

Abstract: A transistor device includes field plate contacts that electrically connect overlying contact pads to field electrodes in underlying trenches, and mesa contacts that electrically connect the contact pads to semiconductor mesas confined by the trenches. Each field plate contact is divided into field plate contact segments that are separated from one another. Each mesa contact is divided into mesa contact segments that are separated from one another. In a first area adjacent to an end of the trenches, a first line that runs perpendicular to the trenches intersects a first field plate contact segment of the field plate contacts and a first mesa contact segment of the mesa contacts. In a second area spaced inward from the first area, a second line that runs perpendicular to the trenches intersects a second field plate contact segment of the field plate contacts and a second mesa contact segment of the mesa contacts.

Abstract: A power semiconductor die has a semiconductor body, an insulation layer on the semiconductor body, a passivation structure arranged above the insulation layer so as to expose a first insulation layer subsection that extends to an edge of the power semiconductor die, and an interruption structure in the first insulation layer subsection.

Abstract: The application relates to a semiconductor transistor device, having a source region, a body region including a channel region extending in a vertical direction, a drain region, a gate region arranged aside the channel region in a lateral direction, and a body contact region made of an electrically conductive material, wherein the body contact region forms a body contact area, the body contact region being in an electrical contact with the body region via the body contact area, and wherein the body contact area is tilted with respect to the vertical direction and the lateral direction.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface over which a plurality of die pads and at least one alignment pad for optical process control for semiconductor wafer probing are arranged. The alignment pad has a hardness smaller than a hardness of the plurality of die pads.

Abstract: The application relates to a semiconductor die having a semiconductor body including an active region, an insulation layer on the semiconductor body, and a sodium stopper formed in the insulation layer. The sodium stopper is arranged in an insulation layer groove which intersects the insulation layer vertically and extends around the active region. The sodium stopper is formed of a tungsten material filling the insulation layer groove.

Abstract: A semiconductor wafer has a semiconductor body, an insulation layer on the semiconductor body, a scribeline region designated to be subjected to a wafer separation processing stage, and an optically detectable reference feature laterally spaced inward from the scribeline region and configured to serve as a reference position during the wafer separation processing stage. A corresponding method of processing the semiconductor wafer, a power semiconductor die and a semiconductor wafer separation apparatus are also described.