Patents by Inventor Oliver Dernovsek

Oliver Dernovsek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10980105
    Abstract: The present invention relates to a carrier (2) with a passive cooling function for a semiconductor component (3), having a main body (6) with a top side (7) and a bottom side (8) and at least one electrical component (13, 13a, 13b) that is embedded in the main body (6), wherein the carrier (2) has a first thermal via (14), which extends from the top side (7) of the main body (6) to the at least one electrical component (13, 13a, 13b), wherein the carrier (2) has a second thermal via (15), which extends from the at least one electrical component (13, 13a, 13b) to the bottom side (8) of the main body (6), and wherein the at least one embedded electrical component (13, 13a, 13b) is electrically contacted by the first and the second thermal via (14, 15).
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: April 13, 2021
    Assignees: TDK Electroncis AG, AT&S Austria Technologie & Systemtechnik AG
    Inventors: Thomas Feichtinger, Oliver Dernovsek, Franz Rinner, Christian Vockenberger
  • Patent number: 10225965
    Abstract: What is specified is an electronic component (100) comprising a functional body (1) provided with a reflection structure (2) wherein the reflection structure (2) is arranged and designed to reflect radiation that impinges on the electronic component (100) from outside away from the functional body (1) and wherein the electronic component (100) is radiation-passive.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: March 5, 2019
    Assignee: EPCOS AG
    Inventors: Oliver Dernovsek, Thomas Feichtinger
  • Patent number: 10014459
    Abstract: A light-emitting diode device is specified, comprising at least one carrier and a light-emitting diode arranged thereon. The carrier comprises a plurality of polymer layers arranged one above another. At least one polymer layer has a cutout, in which an electrical component is embedded.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: July 3, 2018
    Assignee: EPCOS AG
    Inventors: Thomas Feichtinger, Oliver Dernovsek
  • Publication number: 20180070436
    Abstract: The present invention relates to a carrier (2) with a passive cooling function for a semiconductor component (3), having a main body (6) with a top side (7) and a bottom side (8) and at least one electrical component (13, 13a, 13b) that is embedded in the main body (6), wherein the carrier (2) has a first thermal via (14), which extends from the top side (7) of the main body (6) to the at least one electrical component (13, 13a, 13b), wherein the carrier (2) has a second thermal via (15), which extends from the at least one electrical component (13, 13a, 13b) to the bottom side (8) of the main body (6), and wherein the at least one embedded electrical component (13, 13a, 13b) is electrically contacted by the first and the second thermal via (14, 15).
    Type: Application
    Filed: March 1, 2016
    Publication date: March 8, 2018
    Inventors: Thomas FEICHTINGER, Oliver DERNOVSEK, Franz RINNER, Christian VOCKENBERGER
  • Patent number: 9875831
    Abstract: A method for producing a multi-layer varistor component is specified. A main body for the multi-layer varistor component includes a plurality of internal electrodes. The method further includes providing the main body with a starting material for a copper electrode layer in such a way that the starting material is directly connected to at least one internal electrode. A thermal treatment of the starting material is performed under a protective gas atmosphere in order to form the copper electrode layer.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 23, 2018
    Assignee: EPCOS AG
    Inventors: Oliver Dernovsek, Jutta Koholka
  • Patent number: 9825212
    Abstract: A piezoelectric multilayer component having a stack of sintered piezoelectric layers and inner electrodes arranged between the piezoelectric layers. A region which has poling cracks is present on the surface of at least one electrode, and the poling cracks are separated from a surface of at least one of the inner electrodes by the region having the poling cracks.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: November 21, 2017
    Assignee: EPCOS AG
    Inventors: Alexander Glazunov, Oliver Dernovsek
  • Publication number: 20170309802
    Abstract: A light-emitting diode device is specified, comprising at least one carrier and a light-emitting diode arranged thereon. The carrier comprises a plurality of polymer layers arranged one above another. At least one polymer layer has a cutout, in which an electrical component is embedded.
    Type: Application
    Filed: August 5, 2015
    Publication date: October 26, 2017
    Applicant: EPCOS AG
    Inventors: Thomas Feichtinger, Oliver Dernovsek
  • Patent number: 9734948
    Abstract: An electronic component has a main body. The main body includes a porous material having surface pores at a surface of the main body. A passivation liquid is arranged in the surface pores. A method of forming an electronic component is also disclosed as is a method of passivating a body.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: August 15, 2017
    Assignee: EPCOS AG
    Inventors: Oliver Dernovsek, Michael Stahl
  • Publication number: 20170006741
    Abstract: What is specified is an electronic component (100) comprising a functional body (1) provided with a reflection structure (2) wherein the reflection structure (2) is arranged and designed to reflect radiation that impinges on the electronic component (100) from outside away from the functional body (1) and wherein the electronic component (100) is radiation-passive.
    Type: Application
    Filed: November 25, 2014
    Publication date: January 5, 2017
    Applicant: EPCOS AG
    Inventors: Oliver DERNOVSEK, Thomas FEICHTINGER
  • Publication number: 20160314880
    Abstract: A method for producing a multi-layer varistor component is specified. A main body for the multi-layer varistor component includes a plurality of internal electrodes. The method further includes providing the main body with a starting material for a copper electrode layer in such a way that the starting material is directly connected to at least one internal electrode. A thermal treatment of the starting material is performed under a protective gas atmosphere in order to form the copper electrode layer.
    Type: Application
    Filed: May 20, 2014
    Publication date: October 27, 2016
    Inventors: Oliver DERNOVSEK, Jutta KOHOLKA
  • Patent number: 9449958
    Abstract: A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: September 20, 2016
    Assignee: EPCOS AG
    Inventors: Thomas Feichtinger, Oliver Dernovsek, Klaus-Dieter Aichholzer, Sebastian Brunner
  • Patent number: 9418980
    Abstract: A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: August 16, 2016
    Assignee: EPCOS AG
    Inventors: Thomas Feichtinger, Oliver Dernovsek, Klaus-Dieter Aichholzer, Sebastian Brunner
  • Publication number: 20160233409
    Abstract: A method for producing a piezoelectric multilayer component is disclosed. Piezoelectric green films and electrode material are provided, arranged alternately on top of one another and sintered. The electrode material is provided with a PbO-containing coating and/or PbO is mixed into the electrode material.
    Type: Application
    Filed: April 19, 2016
    Publication date: August 11, 2016
    Inventors: Alexander Glazunov, Oliver Dernovsek
  • Patent number: 9343652
    Abstract: A method for producing a piezoelectric multilayer component is disclosed. Piezoelectric green films and electrode material are provided, arranged alternately on top of one another and sintered. The electrode material is provided with a PbO-containing coating and/or PbO is mixed into the electrode material.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: May 17, 2016
    Assignee: EPCOS AG
    Inventors: Alexander Glazunov, Oliver Dernovsek
  • Patent number: 9337408
    Abstract: A light-emitting diode device has a first carrier and at least one light-emitting diode chip, which is arranged on the first carrier. The first carrier has at least one first and one second carrier part, wherein the light-emitting diode chip rests only on the first carrier part. Furthermore, the first and second carrier parts each have a thermal conductivity. The thermal conductivity of the first carrier part is at least 1.5 times the thermal conductivity of the second carrier part. The first carrier part is surrounded laterally by the second carrier part.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: May 10, 2016
    Assignee: EPCOS AG
    Inventors: Thomas Feichtinger, Sebastian Brunner, Oliver Dernovsek, Klaus-Dieter Aichholzer, Georg Krenn, Axel Pecina, Christian Faistauer
  • Publication number: 20160071648
    Abstract: An electronic component has a main body. The main body includes a porous material having surface pores at a surface of the main body. A passivation liquid is arranged in the surface pores. A method of forming an electronic component is also disclosed as is a method of passivating a body.
    Type: Application
    Filed: April 4, 2014
    Publication date: March 10, 2016
    Inventors: Oliver Dernovsek, Michael Stahl
  • Patent number: 9209619
    Abstract: An ESD protection component includes a ceramic material and a BGA or LGA termination. In addition, an ESD protection component includes a basic body with a lower side. The basic body includes a ceramic material. At least one floating inner electrode is located at a distance from the lower side of two to 100 ceramic grains. Also a component includes a carrier, on which an LED and an ESD protection component are arranged.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 8, 2015
    Assignee: EPCOS AG
    Inventors: Thomas Feichtinger, Oliver Dernovsek
  • Patent number: 9209382
    Abstract: A piezo electrical component has a stack of piezo electrical layers arranged over each other and electrode layers arranged therebetween. The stack has at least one first piezo electrical layer having a first piezo electrical charge constant and, directly adjacent thereto, at least one second piezo electrical layer having a second piezo electrical charge constant. The piezo electrical charge constant describes an expansion of the piezo electrical layer perpendicular to an electrical field at a voltage 6 applied to the electrode layers. The first piezo electrical charge constant is different from the second piezo electrical charge constant.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: December 8, 2015
    Assignee: EPCOS AG
    Inventors: Alexander Glazunov, Oliver Dernovsek
  • Publication number: 20150243865
    Abstract: A light-emitting diode device has a first carrier and at least one light-emitting diode chip, which is arranged on the first carrier. The first carrier has at least one first and one second carrier part, wherein the light-emitting diode chip rests only on the first carrier part. Furthermore, the first and second carrier parts each have a thermal conductivity. The thermal conductivity of the first carrier part is at least 1.5 times the thermal conductivity of the second carrier part. The first carrier part is surrounded laterally by the second carrier part.
    Type: Application
    Filed: July 22, 2013
    Publication date: August 27, 2015
    Inventors: Thomas Feichtinger, Sebastian Brunner, Oliver Dernovsek, Klaus-Dieter Aichholzer, Georg Krenn, Axel Pecina, Christian Faistauer
  • Publication number: 20150144983
    Abstract: A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip, arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.
    Type: Application
    Filed: April 17, 2013
    Publication date: May 28, 2015
    Inventors: Thomas Feichtinger, Oliver Dernovsek, Klaus-Dieter Aichholzer, Sebastian Brunner