Patents by Inventor Olivier Rayssac

Olivier Rayssac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10002763
    Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing a support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the semiconductor substrate.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: June 19, 2018
    Assignee: Soitec
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
  • Patent number: 8991673
    Abstract: An automatic cutting device is described for cutting an assembly. The assembly includes a material having a weakened zone therein that defines a useful layer and being attached to a source substrate. The cutting device includes a cutting mechanism and a holding and positioning mechanism operatively associated with the cutting mechanism. The holding and positioning mechanism positions the material so that the cutting mechanism detaches the layer from the source substrate along the weakened zone. The cutting device also includes a control mechanism for adjusting at least two different portions of the assembly during detachment of the layer to facilitate a more precise detachment.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: March 31, 2015
    Assignee: Soitec
    Inventors: Olivier Rayssac, Fabrice Letertre
  • Patent number: 8252664
    Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing an support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the substrate.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: August 28, 2012
    Assignee: Soitec
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
  • Publication number: 20120058621
    Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing an support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the substrate.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 8, 2012
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
  • Publication number: 20120048906
    Abstract: An automatic cutting device is described for cutting an assembly. The assembly includes a material having a weakened zone therein that defines a useful layer and being attached to a source substrate. The cutting device includes a cutting mechanism and a holding and positioning mechanism operatively associated with the cutting mechanism. The holding and positioning mechanism positions the material so that the cutting mechanism detaches the layer from the source substrate along the weakened zone. The cutting device also includes a control mechanism for adjusting at least two different portions of the assembly during detachment of the layer to facilitate a more precise detachment.
    Type: Application
    Filed: November 10, 2011
    Publication date: March 1, 2012
    Inventors: Olivier Rayssac, Fabrice Letertre
  • Publication number: 20120012048
    Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing an support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the substrate.
    Type: Application
    Filed: September 27, 2011
    Publication date: January 19, 2012
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
  • Patent number: 8093687
    Abstract: Methods for transferring of a useful layer from a support are described. In an embodiment, the method includes for facilitating transfer of a useful layer from a support by providing an interface in a first support to define a useful layer; and forming a peripheral recess on the first support below the interface so that the periphery of the interface is exposed to facilitate removal and transfer of the useful layer. An epitaxial layer can be formed on the useful layer after forming the recess, with the width and depth of the recess being sufficient to accommodate the volume of residual material resulting from formation of the epitaxial layer without covering the periphery of the interface. Alternatively, an epitaxial layer can be formed on the useful layer after forming the recess, wherein the peripheral recess is configured for receiving sufficient residual material from the epitaxial layer to prevent bonding between the residual material and the useful layer.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Olivier Rayssac
  • Patent number: 8083115
    Abstract: An automatic cutting device is described for cutting an assembly. The assembly includes a material having a weakened zone therein that defines a useful layer and being attached to a source substrate. The cutting device includes a cutting mechanism and a holding and positioning mechanism operatively associated with the cutting mechanism. The holding and positioning mechanism positions the material so that the cutting mechanism detaches the layer from the source substrate along the weakened zone. The cutting device also includes a control mechanism for adjusting at least two different portions of the assembly during detachment of the layer to facilitate a more precise detachment.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: December 27, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Olivier Rayssac, Fabrice Letertre
  • Publication number: 20110233733
    Abstract: The invention relates to a release substrate produced from semiconductor materials, and which includes a first substrate release layer having a surface in contact with a connecting layer, and a second substrate release layer having a surface in contact with the connecting layer opposite the first substrate release layer so that the connecting layer is located between the first substrate release layer and second substrate release layer; and a concentrated zone of solid nanoparticles located within the connecting layer to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment while also facilitating breaking of the connecting layer by mechanical action.
    Type: Application
    Filed: June 2, 2011
    Publication date: September 29, 2011
    Inventors: Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac, Takeshi Akatsu
  • Patent number: 8012289
    Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: September 6, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative, Takeshi Akatsu
  • Publication number: 20110171812
    Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal expansion of the support substrate and of the working layer. In another embodiment, the method includes providing a source substrate with a weakened zone defining a nucleation layer, bonding a support substrate to the source substrate, detaching the nucleation layer and support substrate at the weakened zone by applying laser irradiation stress, depositing a semiconductor material upon the nucleation layer, bonding a target substrate to the deposited layer and removing the support substrate and nucleation layer. The result is a semiconductor substrate that includes the layer of semiconductor material on a support or target substrate.
    Type: Application
    Filed: January 5, 2011
    Publication date: July 14, 2011
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
  • Patent number: 7972939
    Abstract: A method for minimizing or avoiding contamination of a receiving handle wafer during transfer of a thin layer from a donor wafer. This method includes providing a donor wafer and a receiving handle wafer, each having a first surface prepared for bonding and a second surface, with the donor wafer providing a layer of material to be transferred to the receiving handle wafer. Next, at least one of the first surfaces is treated to provide increased bonding energy when the first surfaces are bonded together; the surfaces are then bonded together to form an intermediate multilayer structure; and a portion of the donor wafer is removed to transfer the thin layer to the receiving handle wafer and form the semiconductor structure. This method avoids or minimizes contamination of the second surface of the receiving handle wafer by treating only the first surface of the donor wafer prior to bonding by exposure to a plasma, and by conducting any thermal treatments after plasma activation at a temperature of 300° C.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: July 5, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Sébastien Kerdiles, Christophe Maleville, Fabrice Letertre, Olivier Rayssac
  • Patent number: 7939428
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: May 10, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
  • Patent number: 7902038
    Abstract: The invention relates to a method for production of a detachable substrate, comprising a method step for the production of an interface by means of fixing, using molecular adhesion, one face of a layer on one face of a substrate, in which, before fixing, a treatment stage for at least one of said faces is provided, rendering the mechanical hold at the interface at such a controlled level to be compatible with a subsequent detachment.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: March 8, 2011
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Bernard Aspar, Hubert Moriceau, Olivier Rayssac, Bruno Ghyselen
  • Patent number: 7892946
    Abstract: A method is presented for cutting an assembly that includes two layers of material having a first surface and a second surface. The method includes providing a weakened interface between the two layers that defines an interface ring about the periphery of the assembly, providing a high-pressure zone at the interface ring, and providing at least one controllable low-pressure zone in the vicinity of at least one of the first surface and the second surface. The technique also includes supplying the high-pressure zone with a controllable high-pressure force, and attacking the interface ring with at least one mechanical force in combination with the high-pressure force to cut the assembly.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: February 22, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Olivier Rayssac, Fabrice Letertre
  • Publication number: 20110039368
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Application
    Filed: October 28, 2010
    Publication date: February 17, 2011
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
  • Patent number: 7888235
    Abstract: A method for fabricating a semiconductor substrate. In an embodiment, this method includes the steps of transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal expansion of the support substrate and of the working layer. The result is a semiconductor substrate that includes the at least one layer of semiconductor material on a support substrate.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: February 15, 2011
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
  • Patent number: 7839001
    Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: November 23, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Giséle Rayssac, legal representative
  • Patent number: 7713369
    Abstract: The invention relates to the preparation of a thin layer comprising a step in which an interface is created between a layer used to create said thin layer and a substrate, characterized in that said interface is made in such a way that it is provided with at least one first zone (Z1) which has a first level of mechanical strength, and a second zone (Z2) which has a level of mechanical strength which is substantially lower than that of the first zone. Said interface can be created by glueing surfaces which are prepared in a differentiated manner, by a layer which is buried and embrittled in a differentiated manner in said zones, or by an intermediate porous layer.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: May 11, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bernard Aspar, Hubert Moriceau, Marc Zussy, Olivier Rayssac
  • Patent number: 7670929
    Abstract: The invention provides methods of direct bonding substrates at least one of which includes a layer of semiconductor material that extends over its front face or in the proximity thereof. The provided methods include, prior to bonding, subjecting the bonding face of at least one substrate comprising a semiconductor material to selected heat treatment at a selected temperature and in a selected gaseous atmosphere. The bonded substrates are useful for electronic, optic, or optoelectronic applications.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: March 2, 2010
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Konstantin Bourdelle, Carlos Mazure, Olivier Rayssac, Pierre Rayssac, legal representative, Giséle Rayssac, legal representative