Patents by Inventor Olivier Rayssac
Olivier Rayssac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7279779Abstract: A substrate-assembly having a mechanical stress absorption system. The assembly includes two substrates, one of which has a mechanical stress absorbing system, such as a plurality of motifs that absorb thermoelastic stresses, to prevent cracking or destruction of the substrates or separation of one substrate from the other.Type: GrantFiled: April 27, 2006Date of Patent: October 9, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
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Patent number: 7276428Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface, implanting atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer, and bonding the free surface of the second layer to a host wafer. The method also includes supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer, conducting a bond strengthening step on the structure after detachment at a temperature of less than about 800° C. to improve the strength of the bond between the second layer and the host wafer, and selectively etching the first layer portion to remove it from the structure and to expose a surface of the second layer.Type: GrantFiled: February 16, 2005Date of Patent: October 2, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Nicolas Daval, Takeshi Akatsu, Nguyet-Phuong Nguyen, Olivier Rayssac
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Patent number: 7265029Abstract: Methods for fabricating a semiconductor substrate. In an embodiment, the technique includes providing an intermediate support, providing a nucleation layer, and providing at least one bonding layer between the intermediate support and the nucleation layer to improve the bonding energy therebetween, and to form an intermediate assembly. The method also includes providing at least one layer of a semiconductor material upon the nucleation layer, bonding a target substrate to the deposited semiconductor material to form a final support assembly comprising the target substrate, the deposited semiconductor material, and the intermediate assembly, and processing the final support assembly to remove the intermediate assembly. The result is a semiconductor substrate that includes the at least one layer of semiconductor material on the target substrate.Type: GrantFiled: July 1, 2004Date of Patent: September 4, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
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Patent number: 7256101Abstract: Methods for preparing a semiconductor assembly are disclosed. In an implementation, the technique includes providing a support substrate and a bonding surface thereon, providing a donor substrate having a weakened zone that defines a useful layer and a bonding surface on the useful layer, and providing an interface layer of a predetermined material on the bonding surface of either the support substrate or the useful layer to provide a bonding surface thereon. The method also includes molecularly bonding the bonding surface of the interface layer to the bonding surface of the other of the support substrate or the useful layer to form a separable bonding interface therebetween, and to thus form the semiconductor assembly, and heat treating the semiconductor assembly to a temperature of at least 1000 to 1100° C.Type: GrantFiled: July 15, 2004Date of Patent: August 14, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
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Publication number: 20070148915Abstract: A method is presented for cutting an assembly that includes two layers of material having a first surface and a second surface. The method includes providing a weakened interface between the two layers that defines an interface ring about the periphery of the assembly, providing a high-pressure zone at the interface ring, and providing at least one controllable low-pressure zone in the vicinity of at least one of the first surface and the second surface. The technique also includes supplying the high-pressure zone with a controllable high-pressure force, and attacking the interface ring with at least one mechanical force in combination with the high-pressure force to cut the assembly.Type: ApplicationFiled: March 2, 2007Publication date: June 28, 2007Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.,Inventors: Olivier Rayssac, Fabrice Letertre
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Patent number: 7235461Abstract: A method for bonding semiconductor structures together is described. The technique includes providing a bonding surface on each of two semiconductor structures, brushing a bonding surface of at least one of the structures to remove contaminants and to activate hydroxyl groups on the bonding surface to enhance hydrophilicity and to facilitate molecular bonding of the structures, and joining the bonding surfaces together by molecular bonding to form a composite structure.Type: GrantFiled: April 27, 2004Date of Patent: June 26, 2007Assignees: S.O.I.Tec Silicon on Insulator Technologies, Commissariat à l'Energie Atomique (CEA)Inventors: Christophe Maleville, Corinne Maunand Tussot, Olivier Rayssac, Sébastien Kerdiles, Benjamin Scarfogliere, Hubert Moriceau, Christophe Morales
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Patent number: 7232738Abstract: A method is presented for cutting an assembly that includes two layers of material having a first surface and a second surface. The method includes providing a weakened interface between the two layers that defines an interface ring about the periphery of the assembly, providing a high-pressure zone at the interface ring, and providing at least one controllable low-pressure zone in the vicinity of at least one of the first surface and the second surface. The technique also includes supplying the high-pressure zone with a controllable high-pressure force, and attacking the interface ring with at least one mechanical force in combination with the high-pressure force to cut the assembly.Type: GrantFiled: July 6, 2004Date of Patent: June 19, 2007Assignee: S.O.I. Tec Silicon on Insulator Technologies S.A.Inventors: Olivier Rayssac, Fabrice Letertre
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Publication number: 20070119893Abstract: An automatic cutting device is described for cutting an assembly. The assembly includes a material having a weakened zone therein that defines a useful layer and being attached to a source substrate. The cutting device includes a cutting mechanism and a holding and positioning mechanism operatively associated with the cutting mechanism. The holding and positioning mechanism positions the material so that the cutting mechanism detaches the layer from the source substrate along the weakened zone. The cutting device also includes a control mechanism for adjusting at least two different portions of the assembly during detachment of the layer to facilitate a more precise detachment.Type: ApplicationFiled: January 11, 2007Publication date: May 31, 2007Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Olivier Rayssac, Fabrice Letertre
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Publication number: 20070122926Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch located below the weakened area. The positioning member maintains the position of the substrate on a moveable support. A cutting mechanism having at least one blade is provided for contacting the substrate and inducing a cleaving wave therein. The cutting mechanism is operatively associated with the positioning member so that the as at least one blade contacts the annular notch, the positioning member prevents movement of the substrate and the moveable support moves away from the substrate to allow the cleaving wave to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.Type: ApplicationFiled: January 30, 2007Publication date: May 31, 2007Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cecile Berne, Olivier Rayssac
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Publication number: 20070104240Abstract: A method for producing a semiconductor entity is described. The method includes providing a donor substrate having a zone of weakness at a predetermined depth to define a thin layer, and the donor substrate includes a bonding interface. A receiver substrate is also provided that includes at least one motif on its surface. The technique further includes bonding the donor substrate at the bonding interface to the at least one motif on the receiver substrate, and supplying sufficient energy to detach a portion of the thin layer from the donor substrate located at the at least one motif and to rupture bonds within the thin layer. The energy thus supplied is insufficient to rupture the bond at the bonding interface. Also described is fabrication of a wafer and the use of the method to produce chips suitable for use in electronics, optics, or optoelectronics applications.Type: ApplicationFiled: December 28, 2006Publication date: May 10, 2007Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Yves Le Vaillant, Olivier Rayssac, Christophe Fernandez
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Publication number: 20070077729Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.Type: ApplicationFiled: July 5, 2006Publication date: April 5, 2007Inventors: Olivier Rayssac, Takeshi Akatsu, Pierre Rayssac, Gisele Rayssac
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Patent number: 7189304Abstract: An automatic high-precision layer cutting device for separating a layer from a semiconductor substrate. The cutting device includes a fixed positioning member for receiving at least a portion of a semiconductor substrate that has a weakened area therein and a peripheral annular notch that is located below the weakened area. The positioning member maintains a predetermined position of the substrate on a support. The device also includes cutting means having at least one blade for contacting the substrate and for inducing a cleaving wave into the substrate. The cutting means is operatively associated with the positioning member so that the at least one blade contacts the annular notch and the positioning member prevents movement of the substrate. The at least one blade induces a cleaving wave of sufficient intensity to both divide the substrate at the notch into first and second parts and detach the layer from the substrate along the weakened area.Type: GrantFiled: October 7, 2003Date of Patent: March 13, 2007Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Muriel Martinez, Thierry Barge, Alain Soubie, Chrystelle Lagahe-Blanchard, Cécile Berne, Olivier Rayssac
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Patent number: 7182234Abstract: An automatic cutting device is described for cutting an assembly. The assembly includes a material having a weakened zone therein that defines a useful layer and being attached to a source substrate. The cutting device includes a cutting mechanism and a holding and positioning mechanism operatively associated with the cutting mechanism. The holding and positioning mechanism positions the material so that the cutting mechanism detaches the layer from the source substrate along the weakened zone. The cutting device also includes a control mechanism for adjusting at least two different portions of the assembly during detachment of the layer to facilitate a more precise detachment.Type: GrantFiled: July 1, 2004Date of Patent: February 27, 2007Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Olivier Rayssac, Fabrice Letertre
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Patent number: 7176554Abstract: A method for producing a semiconductor entity is described. The method includes providing a donor substrate having a zone of weakness at a predetermined depth to define a thin layer, and the donor substrate includes a bonding interface. A receiver substrate is also provided that includes at least one motif on its surface. The technique further includes bonding the donor substrate at the bonding interface to the at least one motif on the receiver substrate, and supplying sufficient energy to detach a portion of the thin layer from the donor substrate located at the at least one motif and to rupture bonds within the thin layer. The energy thus supplied is insufficient to rupture the bond at the bonding interface. Also described is fabrication of a wafer and the use of the method to produce chips suitable for use in electronics, optics, or optoelectronics applications.Type: GrantFiled: June 7, 2004Date of Patent: February 13, 2007Assignee: S.O.I. Tec Silicon on Insulator Technologies S.A.Inventors: Yves Matthieu Le Vaillant, Olivier Rayssac, Christophe Fernandez
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Patent number: 7169683Abstract: A preventive treatment method for a multilayer semiconductor structure having a support substrate, at least one intermediate layer and a surface layer in which the surface layer is to be subjected to a subsequent chemical treatment. The method includes forming a protective layer between the intermediate layer and the surface layer. The protective layer is made from a material chosen to be sufficiently resistant to the chemical treatment to protect the intermediate layer from chemical attack.Type: GrantFiled: October 14, 2003Date of Patent: January 30, 2007Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Bruno Ghyselen, Olivier Rayssac
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Patent number: 7163873Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.Type: GrantFiled: November 28, 2005Date of Patent: January 16, 2007Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
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Patent number: 7145214Abstract: A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.Type: GrantFiled: November 28, 2005Date of Patent: December 5, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac
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Publication number: 20060270187Abstract: A method for minimizing or avoiding contamination of a receiving handle wafer during transfer of a thin layer from a donor wafer. This method includes one step of providing a donor wafer and a receiving handle wafer, each having a first surface prepared for bonding and a second surface, with the donor layer including a zone of weakness that defines a thin layer of donor wafer material to be transferred to the receiving handle wafer. Next, at least one of the first surfaces is treated to provide increased bonding energy when the first surfaces are bonded together; the surfaces are then bonded together to form an intermediate multilayer structure; and the thin layer is transferred to the receiving handle wafer to form a final multilayer structure by detachment at the zone of weakness and removal of remaining material of the donor wafer.Type: ApplicationFiled: May 25, 2005Publication date: November 30, 2006Inventors: Sébastien Kerdiles, Christophe Maleville, Fabrice Letertre, Olivier Rayssac
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Publication number: 20060231203Abstract: Methods for transferring of a useful layer from a support are described. In an embodiment, the method includes for facilitating transfer of a useful layer from a support by providing an interface in a first support to define a useful layer; and forming a peripheral recess on the first support below the interface so that the periphery of the interface is exposed to facilitate removal and transfer of the useful layer. An epitaxial layer can be formed on the useful layer after forming the recess, with the width and depth of the recess being sufficient to accommodate the volume of residual material resulting from formation of the epitaxial layer without covering the periphery of the interface. Alternatively, an epitaxial layer can be formed on the useful layer after forming the recess, wherein the peripheral recess is configured for receiving sufficient residual material from the epitaxial layer to prevent bonding between the residual material and the useful layer.Type: ApplicationFiled: May 22, 2006Publication date: October 19, 2006Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A., a French companyInventors: Fabrice Letertre, Olivier Rayssac
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Patent number: 7122095Abstract: Methods for forming an assembly for transfer of a useful layer are described. In an embodiment, the method includes forming a useful layer on a first support having an interface therebetween, and a residual material on a portion of the first support to form the assembly, and processing the assembly to attenuate any bond between the useful layer and the first support caused by the residual material. An implementation of the method includes processing the assembly to remove residual material. In another variation, processing of the assembly includes forming at least one cut or separating channel between a free surface of the useful layer and the interface to separate the useful layer from contact with the residual material. In yet another variation, processing of the assembly includes forming a peripheral recess so that the residual material does not contact the useful layer.Type: GrantFiled: March 11, 2004Date of Patent: October 17, 2006Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.Inventors: Fabrice Letertre, Olivier Rayssac