Patents by Inventor Osamu Arisumi
Osamu Arisumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11950414Abstract: According to one embodiment, a memory device includes a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure and including a semiconductor layer that extends in a direction perpendicular to a surface of the substrate. The semiconductor layer includes a first portion on a side of an upper portion of the structure, and a second portion between the first portion and the substrate. The first portion has a thickness larger than a thickness of the second portion.Type: GrantFiled: November 30, 2020Date of Patent: April 2, 2024Assignee: Kioxia CorporationInventors: Yasuhiro Uchimura, Tatsufumi Hamada, Shinichi Sotome, Tomohiro Kuki, Yasunori Oshima, Osamu Arisumi
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Publication number: 20220077184Abstract: A semiconductor device according to one embodiment includes a substrate, a wiring layer provided on the substrate and including source lines, a stacked body including a plurality of conductive layers and a plurality of insulating layers alternately stacked on the wiring layer, a cell film provided in the stacked body, a semiconductor film facing the cell film in the stacked body, and a diffusion film being in contact with the source lines in the wiring layer and being in contact with the semiconductor film in the stacked body. The diffusion film includes impurities and a top end portion of the diffusion film is at a higher position than a lowermost conductive layer among the conductive layers.Type: ApplicationFiled: June 17, 2021Publication date: March 10, 2022Applicant: Kioxia CorporationInventors: Atsushi FUKUMOTO, Junya FUJITA, Osamu ARISUMI, Fan WEN, Takayuki ITO
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Publication number: 20210082940Abstract: According to one embodiment, a memory device includes a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure and including a semiconductor layer that extends in a direction perpendicular to a surface of the substrate. The semiconductor layer includes a first portion on a side of an upper portion of the structure, and a second portion between the first portion and the substrate. The first portion has a thickness larger than a thickness of the second portion.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Yasuhiro UCHIMURA, Tatsufumi HAMADA, Shinichi SOTOME, Tomohiro KUKI, Yasunori OSHIMA, Osamu ARISUMI
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Patent number: 10490565Abstract: According to one embodiment, the source layer includes a semiconductor layer including a dopant. The columnar portions are disposed in an area between the separation portions. The columnar portions extend in the stacking direction through the stacked body and through the semiconductor layer. The columnar portions include a plurality of semiconductor bodies including sidewall portions contacting the semiconductor layer. The dopant diffusion prevention film is provided inside the semiconductor layer and separated from the columnar portions in an area between the columnar portions. The dopant diffusion prevention film is not provided inside the semiconductor layer in an area between the separation portion and the columnar portions.Type: GrantFiled: July 19, 2019Date of Patent: November 26, 2019Assignee: Toshiba Memory CorporationInventors: Osamu Arisumi, Yusuke Kawano
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Publication number: 20190341397Abstract: According to one embodiment, the source layer includes a semiconductor layer including a dopant. The columnar portions are disposed in an area between the separation portions. The columnar portions extend in the stacking direction through the stacked body and through the semiconductor layer. The columnar portions include a plurality of semiconductor bodies including sidewall portions contacting the semiconductor layer. The dopant diffusion prevention film is provided inside the semiconductor layer and separated from the columnar portions in an area between the columnar portions. The dopant diffusion prevention film is not provided inside the semiconductor layer in an area between the separation portion and the columnar portions.Type: ApplicationFiled: July 19, 2019Publication date: November 7, 2019Applicant: Toshiba Memory CorporationInventors: Osamu ARISUMI, Yusuke KAWANO
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Patent number: 10411028Abstract: According to one embodiment, the source layer includes a semiconductor layer including a dopant. The columnar portions are disposed in an area between the separation portions. The columnar portions extend in the stacking direction through the stacked body and through the semiconductor layer. The columnar portions include a plurality of semiconductor bodies including sidewall portions contacting the semiconductor layer. The dopant diffusion prevention film is provided inside the semiconductor layer and separated from the columnar portions in an area between the columnar portions. The dopant diffusion prevention film is not provided inside the semiconductor layer in an area between the separation portion and the columnar portions.Type: GrantFiled: March 8, 2018Date of Patent: September 10, 2019Assignee: Toshiba Memory CorporationInventors: Osamu Arisumi, Yusuke Kawano
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Publication number: 20190067312Abstract: According to one embodiment, the source layer includes a semiconductor layer including a dopant. The columnar portions are disposed in an area between the separation portions. The columnar portions extend in the stacking direction through the stacked body and through the semiconductor layer. The columnar portions include a plurality of semiconductor bodies including sidewall portions contacting the semiconductor layer. The dopant diffusion prevention film is provided inside the semiconductor layer and separated from the columnar portions in an area between the columnar portions. The dopant diffusion prevention film is not provided inside the semiconductor layer in an area between the separation portion and the columnar portions.Type: ApplicationFiled: March 8, 2018Publication date: February 28, 2019Applicant: Toshiba Memory CorporationInventors: Osamu ARISUMI, Yusuke KAWANO
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Patent number: 9837430Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers, a plurality of insulating layers, the plurality of insulating layers having a side surface, a plurality of first conductive films provided between the plurality of electrode layers and the plurality of insulating layers, the plurality of first conductive films having a side surface, and a blocking insulating film, the blocking insulating film including a first portion and a second portion; and a semiconductor film. The first distance between the semiconductor film and the side surface of the plurality of first conductive films is shorter than a second distance between the semiconductor film and the second portion.Type: GrantFiled: October 29, 2015Date of Patent: December 5, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Osamu Arisumi, Toshihiko Iinuma
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Publication number: 20170069646Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers, a plurality of insulating layers, the plurality of insulating layers having a side surface, a plurality of first conductive films provided between the plurality of electrode layers and the plurality of insulating layers, the plurality of first conductive films having a side surface, and a blocking insulating film, the blocking insulating film including a first portion and a second portion; and a semiconductor film. The first distance between the semiconductor film and the side surface of the plurality of first conductive films is shorter than a second distance between the semiconductor film and the second portion.Type: ApplicationFiled: October 29, 2015Publication date: March 9, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Osamu ARISUMI, Toshihiko IINUMA
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Patent number: 9240494Abstract: A semiconductor device including a first dielectric film, a floating gate portion, second and third dielectric films, a control gate portion, and a recess on the side face of the floating gate portion. The second dielectric film for element isolation is embedded between a height position of a lower portion of the side face of the floating gate portion and a height position inside the semiconductor substrate. The third dielectric film covers an upper surface and a side face portion of the floating gate portion up to a height position of an upper surface of the second dielectric film, and on the second dielectric film. A height position of an interface between the second and third dielectric films is between a height position of a center of the recess and a position in a predetermined range below the height position of the center of the recess.Type: GrantFiled: December 13, 2012Date of Patent: January 19, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Arisumi, Toshihiko Iinuma
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Patent number: 8766350Abstract: A semiconductor device according to an embodiment, includes a plurality of gate structures; a first dielectric film; and a second dielectric film. The first dielectric film crosslinks adjacent gate structures of the plurality of gate structures so as to form a cavity each above and below in a position between the adjacent gate structures. The second dielectric film is formed as if to cover the cavity above the first dielectric film between the adjacent gate structures.Type: GrantFiled: August 15, 2012Date of Patent: July 1, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Arisumi, Toshihiko Iinuma
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Publication number: 20140048863Abstract: A semiconductor device including a first dielectric film, a floating gate portion, second and third dielectric films, a control gate portion, and a recess on the side face of the floating gate portion. The second dielectric film for element isolation is embedded between a height position of a lower portion of the side face of the floating gate portion and a height position inside the semiconductor substrate. The third dielectric film covers an upper surface and a side face portion of the floating gate portion up to a height position of an upper surface of the second dielectric film, and on the second dielectric film. A height position of an interface between the second and third dielectric films is between a height position of a center of the recess and a position in a predetermined range below the height position of the center of the recess.Type: ApplicationFiled: December 13, 2012Publication date: February 20, 2014Inventors: Osamu ARISUMI, Toshihiko Iinuma
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Publication number: 20130240969Abstract: A semiconductor device according to an embodiment, includes a plurality of gate structures; a first dielectric film; and a second dielectric film. The first dielectric film crosslinks adjacent gate structures of the plurality of gate structures so as to form a cavity each above and below in a position between the adjacent gate structures. The second dielectric film is formed as if to cover the cavity above the first dielectric film between the adjacent gate structures.Type: ApplicationFiled: August 15, 2012Publication date: September 19, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Osamu ARISUMI, Toshihiko Iinuma
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Patent number: 8119196Abstract: A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid from the liquid container to the discharge portion using pressurization from the gas supply tube; a first connecting portion capable of attaching and detaching the liquid container to and from the coating liquid supply tube; a second connecting portion capable of attaching and detaching the liquid container to and from the gas supply tube; and a solvent supply tube supplying a solvent, which can dissolve the coating liquid, to the first connecting portion.Type: GrantFiled: February 24, 2010Date of Patent: February 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda
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Patent number: 7884413Abstract: A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-containing polymer on the water-adhered first insulating film, and forming a second insulating film containing silicon oxide as a main ingredient from the polymer solution layer, wherein forming the second insulating film includes forming silicon oxide by a reaction between the polymer and water adhered to the first insulating film.Type: GrantFiled: July 30, 2008Date of Patent: February 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Arisumi, Masahiro Kiyotoshi
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Publication number: 20100159710Abstract: A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid from the liquid container to the discharge portion using pressurization from the gas supply tube; a first connecting portion capable of attaching and detaching the liquid container to and from the coating liquid supply tube; a second connecting portion capable of attaching and detaching the liquid container to and from the gas supply tube; and a solvent supply tube supplying a solvent, which can dissolve the coating liquid, to the first connecting portion.Type: ApplicationFiled: February 24, 2010Publication date: June 24, 2010Inventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda
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Publication number: 20100055869Abstract: A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.Type: ApplicationFiled: October 2, 2009Publication date: March 4, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda, Yoshitaka Tsunashima
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Patent number: 7618876Abstract: A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.Type: GrantFiled: September 16, 2005Date of Patent: November 17, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda, Yoshitaka Tsunashima
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Publication number: 20090206409Abstract: A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-containing polymer on the water-adhered first insulating film, and forming a second insulating film containing silicon oxide as a main ingredient from the polymer solution layer, wherein forming the second insulating film includes forming silicon oxide by a reaction between the polymer and water adhered to the first insulating film.Type: ApplicationFiled: July 30, 2008Publication date: August 20, 2009Inventors: Osamu Arisumi, Masahiro Kiyotoshi
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Patent number: 7527982Abstract: In order to improve the characteristic of the PZT film (insulation film of capacitor) of the PZT capacitor, after forming the amorphous PZT film, the amorphous PZT film is crystallized from at least the upper surface of the amorphous PZT film to form the PZT crystal film by employing the process whose sequence is reverse to that of the conventional process. In this case, the amorphous PZT film, which contains excessive oxygen and formed on the upper surface of the amorphous PZT film, is used as a seed.Type: GrantFiled: July 14, 2000Date of Patent: May 5, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Osamu Arisumi