Patents by Inventor Osamu Arisumi

Osamu Arisumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7514338
    Abstract: A method of manufacturing a semiconductor device, includes preparing a work piece having a trench on its main surface side, forming a polymer film containing a polymer containing silicon, hydrogen and nitrogen on the main surface of the work piece, holding the work piece with the polymer film in a first atmosphere, which contains oxygen, and whose oxygen partial pressure is set in a range of 16 to 48 Torr, oxidizing the polymer film in a second atmosphere containing water vapor to form an oxide film containing a silicon oxide as a main component, after holding the work piece in the first atmosphere, and removing an upper portion of the oxide film to remain a lower portion of the oxide film in the trench.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: April 7, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi
  • Patent number: 7504680
    Abstract: A semiconductor device according to an aspect of the invention includes a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a sidewall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×?/6 [rad]} or less.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: March 17, 2009
    Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies AG
    Inventors: Osamu Arisumi, Yoshinori Kumura, Kazuhiro Tomioka, Ulrich Egger, Haoran Zhuang, Bum-ki Moon
  • Publication number: 20090036629
    Abstract: Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a butanol concentration of 30 ppm or less, and polysilazane perhydride dissolved in the dibutyl ether, subjecting the polysilazane perhydride film to oxidation in an atmosphere containing water vapor to form a silicon dioxide film, and selectively removing the silicon dioxide film to leave the silicon dioxide film in the element isolation trench to form an element isolating insulation film.
    Type: Application
    Filed: June 25, 2008
    Publication date: February 5, 2009
    Inventors: Atsuko Kawasaki, Masahiro Kiyotoshi, Keisuke Nakazawa, Osamu Arisumi, Jakeshi Hoshi, Katsuhiko Tachibana
  • Patent number: 7473565
    Abstract: A semiconductor device comprises a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode and made of a perovskite type ferroelectrics containing Pb, Zr, Ti and O, the dielectric film comprising a first portion formed of a plurality of crystal grains partitioned by grain boundaries having a plurality of directions.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: January 6, 2009
    Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies AG
    Inventors: Osamu Arisumi, Keitaro Imai, Koji Yamakawa, Bum-ki Moon
  • Patent number: 7416955
    Abstract: A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-containing polymer on the water-adhered first insulating film, and forming a second insulating film containing silicon oxide as a main ingredient from the polymer solution layer, wherein forming the second insulating film includes forming silicon oxide by a reaction between the polymer and water adhered to the first insulating film.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: August 26, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi
  • Patent number: 7407864
    Abstract: Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a butanol concentration of 30 ppm or less, and polysilazane perhydride dissolved in the dibutyl ether, subjecting the polysilazane perhydride film to oxidation in an atmosphere containing water vapor to form a silicon dioxide film, and selectively removing the silicon dioxide film to leave the silicon dioxide film in the element isolation trench to form an element isolating insulation film.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: August 5, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kawasaki, Masahiro Kiyotoshi, Keisuke Nakazawa, Osamu Arisumi, Takeshi Hoshi, Katsuhiko Tachibana
  • Publication number: 20080090988
    Abstract: A method for handling polysilazane or a polysilazane solution includes synthesizing polysilazane and preparing the polysilazane solution in a first space isolated from outside air. The first space is mainly supplied with air from which amine, basic substance, volatile organic compound and acidic substance are eliminated.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 17, 2008
    Inventors: Keisuke Nakazawa, Katsuhiko Tachibana, Takeshi Hoshi, Masahiro Kiyotoshi, Atsuko Kawasaki, Osamu Arisumi
  • Patent number: 7259094
    Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: August 21, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Keisuke Nakazawa, Koji Yamakawa, Hiroyuki Kanaya, Yoshinori Kumura, Hiroshi Itokawa, Osamu Arisumi
  • Publication number: 20070166951
    Abstract: A method of manufacturing a semiconductor device, includes preparing a work piece having a trench on its main surface side, forming a polymer film containing a polymer containing silicon, hydrogen and nitrogen on the main surface of the work piece, holding the work piece with the polymer film in a first atmosphere, which contains oxygen, and whose oxygen partial pressure is set in a range of 16 to 48 Torr, oxidizing the polymer film in a second atmosphere containing water vapor to form an oxide film containing a silicon oxide as a main component, after holding the work piece in the first atmosphere, and removing an upper portion of the oxide film to remain a lower portion of the oxide film in the trench.
    Type: Application
    Filed: October 10, 2006
    Publication date: July 19, 2007
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi
  • Publication number: 20070096180
    Abstract: A semiconductor device includes a semiconductor substrate, and a ferroelectric capacitor provided on the semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a first ferroelectric film provided on the lower electrode including Pb(ZrxTi1-x)O3 and having a tetragonal crystal system whose crystal direction is oriented in a <111> direction, a second ferroelectric film provided on the first ferroelectric film including Pb(ZryTi1-y)O3 and having a tetragonal crystal system whose crystal direction is oriented in the <111> direction, and an upper electrode provided on the second ferroelectric film.
    Type: Application
    Filed: September 21, 2006
    Publication date: May 3, 2007
    Inventors: Koji Yamakawa, Soichi Yamazaki, Osamu Hidaka, Osamu Arisumi
  • Publication number: 20060281336
    Abstract: A method of manufacturing a semiconductor device, includes forming a first insulating film containing silicon oxide as a main ingredient, on an underlying region, adhering water to the first insulating film, forming a polymer solution layer containing a silicon-containing polymer on the water-adhered first insulating film, and forming a second insulating film containing silicon oxide as a main ingredient from the polymer solution layer, wherein forming the second insulating film includes forming silicon oxide by a reaction between the polymer and water adhered to the first insulating film.
    Type: Application
    Filed: May 25, 2006
    Publication date: December 14, 2006
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi
  • Publication number: 20060270170
    Abstract: A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.
    Type: Application
    Filed: September 16, 2005
    Publication date: November 30, 2006
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda, Yoshitaka Tsunashima
  • Publication number: 20060231876
    Abstract: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a side wall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×?/6 [rad]} or more.
    Type: Application
    Filed: April 18, 2005
    Publication date: October 19, 2006
    Inventors: Osamu Arisumi, Yoshinori Kumura, Kazuhiro Tomioka, Ulrich Egger, Haoran Zhuang, Bum-ki Moon
  • Publication number: 20060205165
    Abstract: Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a butanol concentration of 30 ppm or less, and polysilazane perhydride dissolved in the dibutyl ether, subjecting the polysilazane perhydride film to oxidation in an atmosphere containing water vapor to form a silicon dioxide film, and selectively removing the silicon dioxide film to leave the silicon dioxide film in the element isolation trench to form an element isolating insulation film.
    Type: Application
    Filed: July 7, 2005
    Publication date: September 14, 2006
    Inventors: Atsuko Kawasaki, Masahiro Kiyotoshi, Keisuke Nakazawa, Osamu Arisumi, Takeshi Hoshi, Katsuhiko Tachibana
  • Patent number: 7105400
    Abstract: There is disclosed a method of manufacturing a semiconductor device, comprising forming an underlying region including an interlevel insulating film on a semiconductor substrate, forming an alumina film on the underlying region, forming a hole in the alumina film, filling the hole with a bottom electrode film, forming a dielectric film on the bottom electrode film, and forming a top electrode film on the dielectric film.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: September 12, 2006
    Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies, AG
    Inventors: Keitaro Imai, Koji Yamakawa, Hiroshi Itokawa, Katsuaki Natori, Osamu Arisumi, Keisuke Nakazawa, Bum-ki Moon
  • Publication number: 20060194405
    Abstract: A semiconductor device has an element isolating region formed of an insulating film having etching rates different from each other in a side close to an inside wall and a center side of a trench formed on a semiconductor substrate, and a selective epitaxial layer formed in both sides of the element isolating region, wherein the element isolating region has a tip portion in a tapered shape or a stepwise shape of which a width becomes narrower at a side closer to the tip portion.
    Type: Application
    Filed: November 4, 2005
    Publication date: August 31, 2006
    Inventors: Hajime Nagano, Kiyotaka Miyano, Osamu Arisumi
  • Publication number: 20060134928
    Abstract: A semiconductor manufacturing apparatus comprises a discharge portion discharging a coating liquid onto a substrate; a gas supply tube supplying an inert gas into a liquid container that contains the coating liquid, and pressurizing an interior of the liquid container; a coating liquid supply tube airtightly supplying the coating liquid from the liquid container to the discharge portion using pressurization from the gas supply tube; a first connecting portion capable of attaching and detaching the liquid container to and from the coating liquid supply tube; a second connecting portion capable of attaching and detaching the liquid container to and from the gas supply tube; and a solvent supply tube supplying a solvent, which can dissolve the coating liquid, to the first connecting portion.
    Type: Application
    Filed: October 11, 2005
    Publication date: June 22, 2006
    Inventors: Osamu Arisumi, Masahiro Kiyotoshi, Katsuhiko Hieda
  • Patent number: 7031138
    Abstract: In a capacitor and a method for its manufacture, a first electrode layer and a second electrode layer are formed such that a ferroelectric layer is situated between the first and second electrode layer. A first bilayer or multi-layer seed structure is formed between the ferroelectric layer and either the first electrode layer or the second electrode layer.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: April 18, 2006
    Assignees: Infineon Technologies AG, Kabushiki Kaisha Toshiba
    Inventors: Bum-Ki Moon, Gerhard Beitel, Osamu Arisumi, Hiroshi Itokawa
  • Publication number: 20050245023
    Abstract: A semiconductor device comprises a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode and made of a perovskite type ferroelectrics containing Pb, Zr, Ti and O, the dielectric film comprising a first portion formed of a plurality of crystal grains partitioned by grain boundaries having a plurality of directions.
    Type: Application
    Filed: July 11, 2005
    Publication date: November 3, 2005
    Inventors: Osamu Arisumi, Keitaro Imai, Koji Yamakawa, Bum-ki Moon
  • Publication number: 20050186767
    Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.
    Type: Application
    Filed: April 21, 2005
    Publication date: August 25, 2005
    Inventors: Katsuaki Natori, Keisuke Nakazawa, Koji Yamakawa, Hiroyuki Kanaya, Yoshinori Kumura, Hiroshi Itokawa, Osamu Arisumi