Patents by Inventor Osamu Arisumi

Osamu Arisumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6924521
    Abstract: A semiconductor device comprises a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode and made of a perovskite type ferroelectrics containing Pb, Zr, Ti and O, the dielectric film comprising a first portion formed of a plurality of crystal grains partitioned by grain boundaries having a plurality of directions.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: August 2, 2005
    Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies AG
    Inventors: Osamu Arisumi, Keitaro Imai, Koji Yamakawa, Bum-ki Moon
  • Publication number: 20050070031
    Abstract: There is disclosed a method of manufacturing a semiconductor device, comprising forming an underlying region including an interlevel insulating film on a semiconductor substrate, forming an alumina film on the underlying region, forming a hole in the alumina film, filling the hole with a bottom electrode film, forming a dielectric film on the bottom electrode film, and forming a top electrode film on the dielectric film.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Keitaro Imai, Koji Yamakawa, Hiroshi Itokawa, Katsuaki Natori, Osamu Arisumi, Keisuke Nakazawa, Bum-ki Moon
  • Publication number: 20050070043
    Abstract: The present invention provides a method for manufacturing a semiconductor device equipped with a capacitor in which a dielectric film is used, wherein a complex oxide is used as a mask material when the dielectric film is etched.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Inventors: Koji Yamakawa, Katsuaki Natori, Soichi Yamazaki, Osamu Arisumi, Hiroshi Itokawa, Hiroyuki Kanaya, Kazuhiro Tomioka, Keisuke Nakazawa, Yasuyuki Taniguchi, Uli Egger
  • Publication number: 20040206995
    Abstract: A semiconductor device comprises a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode and made of a perovskite type ferroelectrics containing Pb, Zr, Ti and O, the dielectric film comprising a first portion formed of a plurality of crystal grains partitioned by grain boundaries having a plurality of directions.
    Type: Application
    Filed: January 21, 2004
    Publication date: October 21, 2004
    Inventors: Osamu Arisumi, Keitaro Imai, Koji Yamakawa, Bum-ki Moon
  • Publication number: 20040155278
    Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.
    Type: Application
    Filed: April 10, 2003
    Publication date: August 12, 2004
    Inventors: Katsuaki Natori, Keisuke Nakazawa, Koji Yamakawa, Hiroyuki Kanaya, Yoshinori Kumura, Hiroshi Itokawa, Osamu Arisumi
  • Publication number: 20040109280
    Abstract: In a capacitor and a method for its manufacture, a first electrode layer and a second electrode layer are formed such that a ferroelectric layer is situated between the first and second electrode layer.
    Type: Application
    Filed: December 9, 2002
    Publication date: June 10, 2004
    Inventors: Bum-Ki Moon, Gerhard Beitel, Osamu Arisumi, Hiroshi Itokawa
  • Patent number: 6351006
    Abstract: A semiconductor device comprises a semiconductor substrate and a capacitor provided above the semiconductor substrate and having an upper electrode, a lower electrode, and a dielectric film provided between the upper electrode and the lower electrode. At least one of the electrodes comprises an SrRuO3 film provided near the dielectric film and a conductive film made of conductive material other than SrRuO3 and provided far from the dielectric film.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: February 26, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Yamakawa, Osamu Arisumi, Katsuhiko Hieda, Tsunetoshi Arikado, Hideyuki Kanai
  • Patent number: 5886385
    Abstract: A semiconductor device comprises: a first semiconductor layer 6 having a first conductivity formed on a substrate having a surface of an insulating material 4; a source region 16a and a drain region 16b, which are formed on the first semiconductor layer so as to be separated from each other and which have a second conductivity different from the first conductivity; a channel region 6 formed on the first semiconductor layer between the source region and the drain region; a gate electrode 10 formed on the channel region a gate sidewall 14 of an insulating material formed on a side of the gate electrode; and a second semiconductor layer 18 having the first conductivity formed on at least the source region. This semiconductor device can effectively suppress the floating-body effect with a simple structure.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: March 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Arisumi, Akira Nishiyama, Makoto Yoshimi
  • Patent number: 5698869
    Abstract: A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: December 16, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Yoshimi, Satoshi Inaba, Atsushi Murakoshi, Mamoru Terauchi, Naoyuki Shigyo, Yoshiaki Matsushita, Masami Aoki, Takeshi Hamamoto, Yutaka Ishibashi, Tohru Ozaki, Hitomi Kawaguchiya, Kazuya Matsuzawa, Osamu Arisumi, Akira Nishiyama