Abstract: A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.

Abstract: Apparatuses, systems, and methods for powered down non-target on-die termination (NT-ODT adjustment). A memory device has NT-ODT powered down logic which couples a designated pin of the command address terminals to an ODT control circuit, bypassing the command decoder, when the memory device is in a powered down state. An NT-ODT adjustment command received along the designated pin causes the ODT control circuit to change a resistance of the termination circuit of the memory while it is in the powered down state.

Abstract: Apparatuses, systems, and methods for access operations during a voltage transition. A memory may receive a system voltage and a clock signal from a controller. The controller may be used to time operations such as write operations however, an internal clock signal of the memory may be dependent on the voltage. The memory operates at a double data rate relative to the clock signal. During a transition period while the voltage changes between levels, the memory may switch to a transition mode where the memory operates at a single data rate.

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: A clock generator circuit may generate internal data clock signals, such as quadrature phase clock signals, based at least in part, on one clock signal responsive, at least in part, to another clock signal. In some examples, the internal data clock signals may be generated from a system clock signal responsive to a data clock signal. In some examples, the internal data clock signal may be generated by sampling the system clock signal. In some examples, the sampling may be performed responsive to the data clock signal. In some examples, a latch may latch a state of the system clock signal responsive to the data clock signal. The latch may output the internal data clock signal.

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: A monitoring unit obtains the performance information of each of a plurality of volumes included in a storage device. A setting unit obtains a performance target value for each of one or more targeted volumes from among the plurality of volumes. Based on the performance information obtained by the monitoring unit and based on a first-type standby time that is attributed to bandwidth limitation of IO requests with respect to the targeted volumes which are obtained by the setting unit and which achieve the performance target value, a bandwidth managing unit obtains the bandwidth for the targeted volumes that achieve the performance target value and performs bandwidth limitation to change the bandwidth of the targeted volumes to the obtained bandwidth.

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

Abstract: A monitoring unit obtains the performance information of each of a plurality of volumes included in a storage device. A setting unit obtains a performance target value for each of one or more targeted volumes from among the plurality of volumes. Based on the performance information obtained by the monitoring unit and based on a first-type standby time that is attributed to bandwidth limitation of IO requests with respect to the targeted volumes which are obtained by the setting unit and which achieve the performance target value, a bandwidth managing unit obtains the bandwidth for the targeted volumes that achieve the performance target value and performs bandwidth limitation to change the bandwidth of the targeted volumes to the obtained bandwidth.

Abstract: A display device includes a first gate signal line and a second gate signal line, and a first drain signal line, a second drain signal line, and a third drain signal line. A first pixel and a second pixel are surrounded by the first gate signal line, the second gate signal line, the first drain signal line, and the second drain signal line, and a third pixel and a fourth pixel are surrounded by the first gate signal line, the second gate signal line, the second drain signal line, and the third drain signal line. A first storage line and a second storage line are disposed between the first gate signal line and the second gate signal line, and the first pixel includes a first thin film transistor connected to the first gate signal line, the first drain signal line, and a first pixel electrode of the first pixel.

Abstract: A display device includes a display area and the terminal area. Formed in the terminal area are FOG terminals connected to external wires and COG input terminals and COG output terminals connected to a semiconductor chip, the FOG terminals being connected to the COG input terminals, the COG output terminals being connected to lead wires extending from wires in the display area. The FOG terminals and the COG input terminals are structured so that a first ITO film is formed on a first terminal metal, the first ITO film having an insulating film formed thereon, the insulating film having first through holes formed therein to expose the first ITO film. The COG output terminals are structured so that the insulating film is formed on a second terminal metal, the insulating film having second through holes formed therein to expose the second terminal metal covered by a second ITO film.

Abstract: A display device includes a first gate signal line and a second gate signal line, and a first drain signal line, a second drain signal line, and a third drain signal line. A first pixel and a second pixel are surrounded by the first gate signal line, the second gate signal line, the first drain signal line, and the second drain signal line, and a third pixel and a fourth pixel are surrounded by the first gate signal line, the second gate signal line, the second drain signal line, and the third drain signal line. A first storage line and a second storage line are disposed between the first gate signal line and the second gate signal line, and the first pixel includes a first thin film transistor connected to the first gate signal line, the first drain signal line, and a first pixel electrode of the first pixel.

Abstract: A display device includes a first gate signal line and a second gate signal line, and a first drain signal line, a second drain signal line, and a third drain signal line. A first pixel and a second pixel are surrounded by the first gate signal line, the second gate signal line, the first drain signal line, and the second drain signal line, and a third pixel and a fourth pixel are surrounded by the first gate signal line, the second gate signal line, the second drain signal line, and the third drain signal line. A first storage line and a second storage line are disposed between the first gate signal line and the second gate signal line, and the first pixel includes a first thin film transistor connected to the first gate signal line, the first drain signal line, and a first pixel electrode of the first pixel.