Abstract: DRAM device enters waiting state of write flag on receiving write command from memory controller via external C/A bus, regulator, and internal C/A bus. On receiving the write flag from the memory controller via write flag signal line, the DRAM device uses the write flag as count start point to start counting a predetermined number of clocks. The DRAM device uses a point at which the predetermined number of clocks have been counted as a taking-in start point of write data to take in the write data propagated through DQ bus. Transmission path of the write flag has topology equal to that of the transmission path of the write data. It can be considered that propagation delays in two transmission paths are equal. By the above defining of the taking-in start point, the DRAM device can appropriately take in the write data regardless of the propagation delay.

Abstract: A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.

Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Abstract: A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.

Abstract: Two types of command interval specifications are defined as first and second command interval specifications. The first command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the second command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command is executed during the column circuits precharge after the preceding command. Therefore, in the case of the second command interval specification, a command interval is substantially shortened. In addition, pairs of banks are defined as bank pairs, and are applied the first and second command interval specifications, so that the DRAM device is small-sized.

Abstract: A method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value or vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the method takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Abstract: DRAM device enters waiting state of write flag on receiving write command from memory controller via external C/A bus, regulator, and internal C/A bus. On receiving the write flag from the memory controller via write flag signal line, the DRAM device uses the write flag as count start point to start counting a predetermined number of clocks. The DRAM device uses a point at which the predetermined number of clocks have been counted as a taking-in start point of write data to take in the write data propagated through DQ bus. Transmission path of the write flag has topology equal to that of the transmission path of the write data. It can be considered that propagation delays in two transmission paths are equal. By the above defining of the taking-in start point, the DRAM device can appropriately take in the write data regardless of the propagation delay.

Abstract: The present invention provides a memory device with a N-MOS self-termination scheme which enables or disables the device to eliminate ringing and line reflections in a memory device such as a DDR SDRAM. The self-termination is achieved by using a weak N-MOS transistor. The N-MOS transistors are within the device and has an impedance of two to eight times of the characteristic impedance of a communication path in a memory device such as DRAM or SRDAM. The communication path is generally a read/write or command/address bus. The self-termination scheme terminates line reflections occurring in a device receiving data during non productive time duration of system clock. The present invention provides a method by which random access memories perform with faster settling time for data inputs and a high system performance.

Abstract: The present invention is a method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions from a low value to a high value of vice versa. The present bit is inverted when the number of transitions is greater than N/2. To avoid the need for having an extra bit accompany data bytes to indicate the presence or absence of inversion, the present invention takes advantage of a data mask pin that is normally unused during writing operations to carry the inversion bit. Non-inverted data is written directly into the memory device while inverted data is first inverted again before writing to storage locations, so that true data is stored in the memory device.

Abstract: Two types of command interval specifications are defined as first and second command interval specifications. The first command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the second command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command is executed during the column circuits precharge after the preceding command. Therefore, in the case of the second command interval specification, a command interval is substantially shortened. In addition, pairs of banks are defined as bank pairs, and are applied the first and second command interval specifications, so that the DRAM device is small-sized.

Abstract: An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.

Abstract: A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.

Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

Abstract: Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bis voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.

Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

Abstract: A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.

Abstract: Switch MOSFETs are interposed between a sense amplifier disposed in a dynamic RAM and complementary bit lines. After signal voltages are read out by selecting operations of word lines from a plurality of dynamic memory cells selected, to the plurality of pairs of complementary bit lines in accordance with individual storage informations, the switch control signal of the switch MOSFETs is changed from a select level to a predetermined intermediate level. This turns on the switch MOSFETs thereby setting sense nodes to one level in accordance with the amplifying operations of the sense amplifier. An amplification signal generated by the amplifying operation is transmitted through the column select circuit to input/output lines in response to the column select signal, and the switch control signal is returned to the select level in response to the selecting operation of the column select circuit.

Abstract: A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.

Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

Abstract: A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.