Patents by Inventor Osamu Nishii

Osamu Nishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200345781
    Abstract: The present invention relates to a cell-based medicine comprising mesenchymal stem cells, and a method for producing the same. More specifically, the present invention relates to: a cell-based medicine containing mesenchymal stem cells, wherein a) the mesenchymal stem cells express CX3CL1 under stimulation with an inflammatory cytokine, and/or b) 90% or more of the mesenchymal stem cells express EGFR and/or ITGA4; and a method for producing a cell-based medicine containing mesenchymal stem cells, the method comprising the steps of: a) adding an inflammatory cytokine to a culture containing mesenchymal stem cells, and confirming that the mesenchymal stem cells express CX3CL1; and/or b) confirming that 90% or more of the mesenchymal stem cells express EGFR and/or ITGA4.
    Type: Application
    Filed: November 9, 2018
    Publication date: November 5, 2020
    Applicants: Sapporo Medical University, Nipro Corporation
    Inventors: Osamu HONMOU, Yoshihiro YOSHIKAWA, Ryo TOMII, Masafumi YAO, Yukari NISHII, Yusuke WAGATSUMA
  • Patent number: 10365979
    Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnosed result.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 30, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Osamu Nishii, Kiwamu Takada
  • Publication number: 20170308445
    Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core 11 and the second CPU core 12 respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Inventors: Osamu NISHII, Kiwamu TAKADA
  • Patent number: 9734023
    Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 15, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Osamu Nishii, Kiwamu Takada
  • Publication number: 20160034368
    Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core 11 and the second CPU core 12 respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.
    Type: Application
    Filed: July 17, 2015
    Publication date: February 4, 2016
    Inventors: Osamu Nishii, Kiwamu Takada
  • Patent number: 8364988
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: January 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
  • Patent number: 8234441
    Abstract: A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory c
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: July 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kunio Uchiyama, Osamu Nishii
  • Patent number: 8145889
    Abstract: A data processor or a data processing system used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. A multiple with which the displacement is multiplied can be changed in accordance with the mode.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: March 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Osamu Nishii
  • Publication number: 20110314213
    Abstract: A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory c
    Type: Application
    Filed: January 18, 2011
    Publication date: December 22, 2011
    Inventors: Kunio UCHIYAMA, Osamu Nishii
  • Publication number: 20110208983
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Application
    Filed: May 5, 2011
    Publication date: August 25, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yonetaro TOTSUKA, Koichiro ISHIBASHI, Hiroyuki MIZUNO, Osamu Nishii, Kunio UCHIYAMA, Takanori SHIMURA, Asako SEKINE, Yoichi KATSUKI, Susumu NARITA
  • Patent number: 7958379
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
  • Patent number: 7904641
    Abstract: A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: March 8, 2011
    Assignee: Renesas Technology Corporation
    Inventors: Kunio Uchiyama, Osamu Nishii
  • Publication number: 20110040954
    Abstract: The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode.
    Type: Application
    Filed: October 27, 2010
    Publication date: February 17, 2011
    Inventor: OSAMU NISHII
  • Patent number: 7836286
    Abstract: The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode.
    Type: Grant
    Filed: January 13, 2008
    Date of Patent: November 16, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Osamu Nishii
  • Publication number: 20100005324
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Application
    Filed: December 30, 2008
    Publication date: January 7, 2010
    Inventors: Yonetaro TOTSUKA, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
  • Patent number: 7475261
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: January 6, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
  • Publication number: 20080229004
    Abstract: A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.
    Type: Application
    Filed: May 19, 2008
    Publication date: September 18, 2008
    Inventors: Kunio UCHIYAMA, Osamu NISHII
  • Publication number: 20080201562
    Abstract: The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode.
    Type: Application
    Filed: January 13, 2008
    Publication date: August 21, 2008
    Inventor: Osamu NISHII
  • Patent number: 7376783
    Abstract: A chip including: a microprocessor; a control unit coupled to the microprocessor; and interface nodes for coupling a synchronous dynamic memory; wherein the control unit generates command information and the interface nodes output the command information to the synchronous dynamic memory in synchronism with a clock signal, wherein the command information includes a mode register set function which sets mode information to a mode register in the synchronous dynamic memory, and wherein the control unit outputs the mode information to address signal input terminals of the synchronous dynamic memory.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: May 20, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kunio Uchiyama, Osamu Nishii
  • Patent number: RE41589
    Abstract: A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: August 24, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Osamu Nishii, Nobuyuki Hayashi, Noriharu Hiratsuka, Tetsuhiko Okada, Hiroshi Takeda