Patents by Inventor Osamu Nishii
Osamu Nishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10365979Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnosed result.Type: GrantFiled: July 10, 2017Date of Patent: July 30, 2019Assignee: Renesas Electronics CorporationInventors: Osamu Nishii, Kiwamu Takada
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Publication number: 20170308445Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core 11 and the second CPU core 12 respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.Type: ApplicationFiled: July 10, 2017Publication date: October 26, 2017Inventors: Osamu NISHII, Kiwamu TAKADA
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Patent number: 9734023Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.Type: GrantFiled: July 17, 2015Date of Patent: August 15, 2017Assignee: Renesas Electronics CorporationInventors: Osamu Nishii, Kiwamu Takada
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Publication number: 20160034368Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core 11 and the second CPU core 12 respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnose result.Type: ApplicationFiled: July 17, 2015Publication date: February 4, 2016Inventors: Osamu Nishii, Kiwamu Takada
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Patent number: 8364988Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: GrantFiled: May 5, 2011Date of Patent: January 29, 2013Assignee: Renesas Electronics CorporationInventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
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Patent number: 8234441Abstract: A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory cType: GrantFiled: January 18, 2011Date of Patent: July 31, 2012Assignee: Renesas Electronics CorporationInventors: Kunio Uchiyama, Osamu Nishii
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Patent number: 8145889Abstract: A data processor or a data processing system used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. A multiple with which the displacement is multiplied can be changed in accordance with the mode.Type: GrantFiled: October 27, 2010Date of Patent: March 27, 2012Assignee: Renesas Electronics CorporationInventor: Osamu Nishii
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Publication number: 20110314213Abstract: A processor system including: a processor having a processor core and a controller core; and a plurality of synchronous memory chips, wherein the processor and the plurality of synchronous memory chips are connected via an external bus; wherein the processor core and the controller core are connected via an internal bus; wherein the plurality of synchronous memory chips are operated according to a clock signal; wherein the controller core comprises a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory cType: ApplicationFiled: January 18, 2011Publication date: December 22, 2011Inventors: Kunio UCHIYAMA, Osamu Nishii
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Publication number: 20110208983Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: ApplicationFiled: May 5, 2011Publication date: August 25, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yonetaro TOTSUKA, Koichiro ISHIBASHI, Hiroyuki MIZUNO, Osamu Nishii, Kunio UCHIYAMA, Takanori SHIMURA, Asako SEKINE, Yoichi KATSUKI, Susumu NARITA
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Patent number: 7958379Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: GrantFiled: December 30, 2008Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
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Patent number: 7904641Abstract: A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.Type: GrantFiled: May 19, 2008Date of Patent: March 8, 2011Assignee: Renesas Technology CorporationInventors: Kunio Uchiyama, Osamu Nishii
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Publication number: 20110040954Abstract: The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode.Type: ApplicationFiled: October 27, 2010Publication date: February 17, 2011Inventor: OSAMU NISHII
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Patent number: 7836286Abstract: The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode.Type: GrantFiled: January 13, 2008Date of Patent: November 16, 2010Assignee: Renesas Electronics CorporationInventor: Osamu Nishii
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Publication number: 20100005324Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: ApplicationFiled: December 30, 2008Publication date: January 7, 2010Inventors: Yonetaro TOTSUKA, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
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Patent number: 7475261Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.Type: GrantFiled: February 2, 2004Date of Patent: January 6, 2009Assignee: Renesas Technology Corp.Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
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Publication number: 20080229004Abstract: A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.Type: ApplicationFiled: May 19, 2008Publication date: September 18, 2008Inventors: Kunio UCHIYAMA, Osamu NISHII
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Publication number: 20080201562Abstract: The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode.Type: ApplicationFiled: January 13, 2008Publication date: August 21, 2008Inventor: Osamu NISHII
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Patent number: 7376783Abstract: A chip including: a microprocessor; a control unit coupled to the microprocessor; and interface nodes for coupling a synchronous dynamic memory; wherein the control unit generates command information and the interface nodes output the command information to the synchronous dynamic memory in synchronism with a clock signal, wherein the command information includes a mode register set function which sets mode information to a mode register in the synchronous dynamic memory, and wherein the control unit outputs the mode information to address signal input terminals of the synchronous dynamic memory.Type: GrantFiled: November 14, 2006Date of Patent: May 20, 2008Assignee: Renesas Technology Corp.Inventors: Kunio Uchiyama, Osamu Nishii
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Publication number: 20080016383Abstract: When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.Type: ApplicationFiled: July 19, 2007Publication date: January 17, 2008Inventors: Takao Watanabe, Kunio Uchiyama, Osamu Nishii, Naohiko Irie, Hiroyuki Mizuno
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Patent number: RE41589Abstract: A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.Type: GrantFiled: November 8, 2002Date of Patent: August 24, 2010Assignee: Renesas Technology Corp.Inventors: Osamu Nishii, Nobuyuki Hayashi, Noriharu Hiratsuka, Tetsuhiko Okada, Hiroshi Takeda