Abstract: A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

Abstract: A signal from a crystal resonator or an external clock signal are input from terminals xta1 or exta1, and the signal from the crystal resonator or external clock signal are selected by mode terminal mod8 and input to an oscillator OSC. An input clock signal ckl1 is frequency-divided to desired values by a divider DIV1. A divided clock signal clk2 is input as the reference clock of a phase-locked loop PLL1 or delay-locked loop DLL1, and a clock signal output by a circuit selected by a selector SEL3 passes via a divider DIV2 to be distributed to an LSI. The phase-locked loop PLL1 has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL1 is 2-3 periods.

Abstract: A small-area associative memory for association by a value resulted from addition, with reduced carry delay, is provided. Adjacent 1-bit memory values and a signal depending on adjacent 2 bits of addition-inputs are inputted into a CAM memory cell constructed using MOS transistors, and a hit line is pulled down or pulled up in accordance with the input values.

Abstract: The invention allows the execution of a PC relative branch instruction with displacement is speeded up without changing the instruction operations of existing processors and without requiring new instructions. The branch target address calculation is made faster by calculating the lower portion of the branch target address prior to storing the instruction word in a cache or buffer, and writing the calculation result into the displacement field of the instruction word and into a bit that has been added to the cache or the buffer, such that some calculation is executed simultaneously to be skipped later at the time of execution of the instruction by using the executed calculation result stored in the cache or buffer.

Abstract: A small-area associative memory for association by a value resulted from addition, with reduced carry delay, is disclosed. Adjacent 1-bit memory values and a signal depending on adjacent 2 bits of addition-inputs are inputted into a CAM memory cell constructed using MOS transistors, and a hit line is pulled down or pulled up in accordance with the input values.

Abstract: A small-area associative memory for association by a value resulted from addition, with reduced carry delay, is disclosed. Adjacent 1-bit memory values and a signal depending on adjacent 2 bits of addition-inputs are inputted into a CAM memory cell constructed using MOS transistors, and a hit line is pulled down or pulled up in accordance with the input values.

Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

Abstract: A small-area associative memory for association by a value resulted from addition, with reduced carry delay, is disclosed. Adjacent 1-bit memory values and a signal depending on adjacent 2 bits of addition-inputs are inputted into a CAM memory cell constructed using MOS transistors, and a hit line is pulled down or pulled up in accordance with the input values.

Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

Abstract: A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

Abstract: A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

Abstract: A data processor in which a speed of an address translating operation is raised is disclosed. A translation lookaside buffer is divided into a buffer for data and a buffer for instruction, address translation information for instruction is also stored into a translation lookaside buffer for data, and when a translation miss occurs in a translation lookaside buffer for instruction, new address translation information is fetched from the translation lookaside buffer for data. A high speed of the address translating operation can be realized as compared with that in case of obtaining address translation information from an external address translation table each time a translation miss occurs in the translation lookaside buffer for instruction.

Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

Abstract: A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, first and second arbiters, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. When a processor requires data from the memory bank, the processor sends a processor ID with a data access request. When the memory bank sends data in return, the memory bank outputs the processor ID of the request originator with the required data. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access requested need not wait for a previous access request to be finished. According, the throughput of the system can be improved greatly. The first and second arbiters serve to decide ownership of buses.

Abstract: A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing. Furthermore, data between the CPU and the FPU is transferred via a communication register. An FPU pipeline is synchronized with a CPU pipeline. The sixteen-bit fixed length instruction group has special instructions for immediate loading of a floating point zero and/or a floating point one. Two instructions are dedicated for this purpose. Furthermore, the 16-bit fixed length instruction group of the FPU flushes denormalized numbers to zero. The instruction set also rounds floating point numbers to zero. An FMAC instruction of the instruction set has the capability to accumulate into a different register for consecutive FMAC operations.

Abstract: The data processor includes a CPU and an instruction prefetch buffer that prefetches an instruction executed by the CPU and stores it therein. The CPU contains a detection circuit for detecting whether or not a displacement from a branch instruction to a branch target instruction is a specific displacement on the basis of branch displacement information that the concerned branch instruction holds. The instruction prefetch buffer clears an instruction already prefetched when the detection circuit detects that the displacement is not the specific displacement and outputs a branch target instruction newly fetched to the CPU, and outputs a branch target instruction already prefetched to the CPU when the detection circuit detects that the displacement is the specific displacement. Thus, the date processor fetches a branch target instruction within a certain range from the instruction prefetch buffer at a high speed without adding the nullifying bit on the instruction code.

Abstract: A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

Abstract: A multiprocessor system includes an address bus 170, a data bus 180, processors 110 and 120, access queues 135 and 145, shared memories 130 and 140, and lock control circuits 500 and 510. Particularly, a lock-in indicative flag register 501 is provided in the lock control circuit 500. While an operand cache 112 in one processor 110 is making a lock access to a predetermined address of the shared memory 130, the flag register 501 is set on the basis of a lock command signal 260 so that an access of an instruction cache 122 in another processor 120 to the predetermined address of the shared memory 130 is prohibited but an access to a different address is permitted at the time of the lock access. After the lock access is released, the lock control circuit 500 accepts an access to the predetermined address.

Abstract: In order to allow prefetching of pointer-type data structure, an instruction word of load instruction has pointer hints indicating that the data being loaded by the instruction comprises a pointer specifying the address of the next data. When a CPU executes such an instruction, and the data requested by that instruction is loaded from a main memory, a prefetch circuit in a memory interface circuit uses this pointer to read a block containing the data specified by this pointer from the main memory, then stores temporarily in a prefetch buffer provided therein. When CPU executes a load instruction requesting reading of the data specified by this pointer, the data in this stored block is supplied to CPU through a processor interface circuit and a cache control circuit.