Abstract: When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

Abstract: A chip including: a microprocessor; a control unit coupled to the microprocessor; and interface nodes for coupling a synchronous dynamic memory; wherein the control unit generates command information and the interface nodes output the command information to the synchronous dynamic memory in synchronism with a clock signal, wherein the command information includes a mode register set function which sets mode information to a mode register in the synchronous dynamic memory, and wherein the control unit outputs the mode information to address signal input terminals of the synchronous dynamic memory.

Abstract: A microprocessor includes a first cache memory, a first instruction fetch unit, a first instruction decoder, a first processing unit and a first latch that holds a control signal outputted from the first instruction decoder. When the first instruction fetch unit receives a first instruction performed by the first processing unit it outputs the first instruction to the first instruction decoder. When the first instruction fetch unit receives a second instruction which is not performed by the first processing unit, it outputs a specific instruction to the first instruction decoder, after which the supply of clock pulses to other latch circuits In the first processing unit is halted based on the control signal.

Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

Abstract: When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

Abstract: When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

Abstract: The invention allows the execution of a PC relative branch instruction with displacement is speeded up without changing the instruction operations of existing processors and without requiring new instructions. The branch target address calculation is made faster by calculating the lower portion of the branch target address prior to storing the instruction word in a cache or buffer, and writing the calculation result into the displacement field of the instruction word and into a bit that has been added to the cache or the buffer, such that some calculation is executed simultaneously to be skipped later at the time of execution of the instruction by using the executed calculation result stored in the cache or buffer.

Abstract: A microprocessor including a first cache memory, a first instruction fetch unit coupled to the first cache memory, a first instruction decoder coupled to the first instruction fetch unit, and a first processing unit coupled to the first instruction decoder, wherein, when the first instruction fetch unit is inputted with a first instruction which is performed by the first processing unit, the first instruction fetch unit outputs the first instruction to the first instruction decoder, wherein when the first instruction fetch unit is inputted with a second instruction which is not performed by the first processing unit, the first instruction fetch unit outputs a specific instruction to the first instruction decoder, and wherein, in the case where the first instruction fetch unit outputs the specific instruction to the first instruction decoder, the supply of clock pulse to the first processing unit is halted.

Abstract: A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.

Abstract: A microprocessor to reduce wasteful power consumption of the floating-point unit. An instruction invalidation logic circuit is utilized to substitute the instruction not-to-use-the-floating-point unit, in the instruction string supplied from the instruction cache, with an invalidating instruction, hold that invalidating instruction in the floating-point register, and supply that invalidating instruction to a floating-point decoder in the floating-point unit. In cases when the invalidating instruction was continuous, the power consumption in the floating-point data path as well as the in the floating-point decoder and floating-point register is reduced.

Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

Abstract: A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.

Abstract: When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

Abstract: An arithmetic unit that performs high speed multiplication and addition operations is provided. The arithmetic unit is applicable to an instruction set not having a multiplication-addition instruction. The arithmetic circuit included in a data processing device is configured to have: a multiplication device (EMUL1) to which data A and B are inputted and which outputs partial signals, sum signal (113) and carry signal (114), for computing A*B; a first addition device (EADD1) which adds the sum signal and the carry signal to compute the final result of A*B; and a second addition device (EADD2) which receives data E, the sum signal, and the carry signal and is capable of computing the result of adding E to A*B. The arithmetic circuit selects among three types of operations, multiplication (A*B), addition (D+E), and multiplication-addition (A*B+E) by selection circuits 104 and 105.

Abstract: A system LSI including substrate-bias generation circuits for supplying substrate biases independent of each other to functional modules integrated in the system LSI, a substrate-bias control circuit for controlling the substrate-bias generation circuits and a substrate-bias control-value storage unit for storing control values to be supplied to the substrate-bias generation circuits. The control values stored in the substrate-bias control-value storage unit are set by carrying out a predetermined operation. As a result, it is possible to provide a device for implementing both a high-speed operation and low power consumption without lowering the yield and for finely controlling the power consumption during the operation.

Abstract: In order to save a sub-threshold leak current during operation of processor, a decision circuit (instruction decoder) inputs an instruction signal and outputs an operation mode signal regarding the level of a leak current based on information about use of the circuit block. Thereby, a sub-threshold leak current in the circuit block not used can be saved.

Abstract: A clock signal generating circuit supplies a clock signal output in a short time of 2-3 clock periods after operation starts. As a result, the clock signal generating circuit can be stopped simultaneously when the operation of an internal circuit is put in a stop state, the clock signal generating circuit can output a clock signal when the internal circuit returns to the operating state, and power consumption when the internal circuit is in the stop state is reduced.

Abstract: A system LSI comprises substrate-bias generation circuits for supplying substrate biases independent of each other to functional modules integrated in the system LSI, a substrate-bias control circuit for controlling the substrate-bias generation circuits and a substrate-bias control-value storage unit for storing control values to be supplied to the substrate-bias generation circuits. The control values stored in the substrate-bias control-value storage unit are set by carrying out a predetermined operation. As a result, it is possible to provide a means for implementing both a high-speed operation and low power consumption without lowering the yield and for finely controlling the power consumption during the operation.