Abstract: A semiconductor device and a formation method thereof are provided. The semiconductor device includes a substrate, an isolation structure, a word line structure, first and second dielectric pillars, and first and second conductive layers. The substrate has an active area and a dummy area. The isolation structure is disposed in the dummy area. The word line structure is disposed in the active area. The first dielectric pillar is disposed on the isolation structure and the word line structure. The second dielectric pillar is disposed on the isolation structure. The first conductive layer is disposed in the active area. The second conductive layer is disposed on the first conductive layer and the second dielectric pillar. The bottom surface of the second conductive layer in the dummy area is lower than the top surface of the first dielectric pillar in the dummy area.

Abstract: A method for forming a semiconductor memory structure includes forming a plurality of conductive wire structures over a semiconductor substrate, and forming a plurality of spacer structures along the sidewalls of the conductive wire structures. Each of the spacer structures includes a first spacer. The method also includes forming a plurality of dielectric strips across the conductive wire structures, forming a plurality of conductive strips over the conductive wire structures and the dielectric strips, performing a patterning process on the conductive strips to form a plurality of conductive pads, and removing the first spacer of each of the spacer structures to form a gap in each of the spacer structures.

Abstract: A quick-lock connector (10) used for a counterpart connector (100) includes a connector body (1), a rotary sleeve (2) and a clockwork spring (3). The rotary sleeve (2) is rotatably disposed around the connector body (1) and includes a latching structure (21) capable of latching the counterpart connector (100). The clockwork spring (3) is nested passes between the connector body (1) and the rotary sleeve (2) for elastically supporting. Thereby, the quick-lock connector (10) has advantages of easy assembling and labor saving.

Abstract: A semiconductor structure includes a substrate, stack structures, first spacers, a contact, and second spacers. The stack structures are located on the substrate and separated from each other. The stack structures include a bit line stack structure and a conductive line stack structure. The first spacers are located on sidewalls of the stack structures. Each of the first spacers includes an oxide layer. The contact is located on the substrate between two adjacent first spacers. The top surface of the oxide layer is not higher than the top surface of the contact. The second spacers are located on the first spacers.

Abstract: Disclosed in the present invention are an anti-seismic component with dual functions of energy consumption and load bearing, and a buffer. The anti-seismic component includes a core shaft, wherein the core shaft is connected to a first support member and a second support member; an overhanging section of the first support member and an overhanging section of the second support member are respectively arranged on two sides of the core shaft; and an included angle between the first support member and the second support member is less than 180°.

Abstract: A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.

Abstract: A non-contact body temperature measuring device includes a temperature measuring unit, a Doppler radar, a processing unit, and a display unit. The temperature measuring unit measures a temperature of a human body in a non-contact manner. The Doppler radar emits radar waves to the human body and receives reflected radar waves. The processing unit, which is electrically connected to the temperature measuring unit and the Doppler radar, determines measurement spots on the human body based on the reflected radar waves, controls the temperature measuring unit to measure temperatures of the measurement spots, and generates a body temperature measuring value based on the temperatures of the measurement spots. The display unit is electrically connected to the processing unit for displaying the body temperature measuring value.

Abstract: Disclosed is a double-knit textile having a plurality of texturized inlay yarns movably positioned between a front layer (112) and a back layer (114) of the double-knit textile. The double-knit textile includes areas where a yarn from the back layer is transferred to the front layer and knitted in one or more knit stitches to form an interknitted location (116). The number of interknitted locations per unit area varies in different portions of the double-knit textile. The double-knit textile is configured to provide zoned insulation and/or cushioning features.

Abstract: The present disclosure provides methods of treating chronic graft-versus-host disease (cGVHID) using an antibody that binds to colony stimulating factor 1 (CSF-1R).

Abstract: A method for searching a path by using a 3D reconstructed map includes: receiving 3D point-cloud map information and 3D material map information; clustering the 3D point-cloud map information with a clustering algorithm to obtain clustering information, and identifying material attributes of objects in the 3D point-cloud map information with a material neural network model to obtain material attribute information; fusing the those map information based on their coordinate information, thereby outputting fused map information; identifying obstacle areas and non-obstacle areas in the fused map information based on an obstacle neural network model, the clustering information, and the material attribute information; and generating 3D path information according to the non-obstacle areas. Since the 3D path information is generated based on those map information, the obstacle areas and flight spaces are effectively determined to generate an accurate flight path.

Abstract: A memory device and a manufacturing method are provided. The memory device includes active regions defined in a semiconductor substrate by an isolation structure, wherein the active regions are arranged as an array along first and second directions, and extend along a third direction; and word lines, extending through the active regions along the second direction in the semiconductor substrate. The active regions are arranged in pairs along the second direction. The active regions in the same pair are closely adjacent to each other by a first spacing. Adjacent pairs of the active regions are separated by a greater second spacing. A featured portion of each active region below an intersecting word line has a first side closely adjacent to the other active region in the same pair by the first spacing and a second side separated from another pair of the active regions by the second spacing, and has an inclined top surface ascending from the second side to the first side.

Abstract: A multiplexer includes a first circuit board, a second circuit board, and a third circuit board. The first circuit board includes a first metal layer, a first substrate layer, and a second metal layer sequentially stacked along a first direction. The second circuit board includes a third metal layer, a second substrate layer, and a fourth metal layer sequentially stacked along the first direction. The third circuit board includes a fifth metal layer, a third substrate layer, and a sixth metal layer sequentially stacked along the first direction. The second and third metal layer have same wiring structure, and the second metal layer connects to the third metal layer to form a first signal transmission path structure and a filter structure. The fourth and fifth metal layer have same wiring structure, and the fourth metal layer connects to the fifth metal layer to form a second signal transmission path structure.

Abstract: A device and a method for detecting a light irradiating angle are disclosed. The device, used to detect the incident direction of a light ray, includes a solar sensor and a processor. The sensing unit of the solar sensor has sensing areas. The sensing areas correspondingly generate sensing signals based on the intensity of the light ray. A mask covers the sensing unit and has an X-shaped light transmitting portion. The light ray transmits the X-shaped light transmitting portion to form an X-axis light ray and a Y-axis light ray. The X-axis light ray intersects the Y-axis light ray. The X-axis light ray and the Y-axis light ray fall on the sensing area. The processor, coupled to the sensing unit, receives the sensing signals and determines information of the incident direction according to the sensing signals.

Abstract: An inspection system with a thermal interface, and an electronic component inspection device and method are provided. First, a temperature regulator contacts an electronic component to be tested, where there is a thermal interface between the temperature regulator and the electronic component to be tested, and the electronic component to be tested includes a plurality of temperature sensing units. Then, the temperature regulator heats or cools the electronic component to be tested to a specific temperature, and the plurality of temperature sensing units of the electronic component to be tested detect temperatures at locations of the temperature sensing units. In this way, a contact condition between the temperature regulator and the electronic component to be tested, and quality or an aging status of the thermal interface can be determined.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.

Abstract: Some demonstrative embodiments include apparatuses, systems and/or methods of communicating a Single-User (SU) Multiple-Input-Multiple-Output (MIMO) transmission. For example, a first wireless communication station may be configured to transmit a Request to Send (RTS) to a second wireless communication station via a plurality of SU MIMO Transmit (Tx) sectors of the first wireless communication station, the RTS to establish a Transmit Opportunity (TXOP) to transmit an SU-MIMO transmission to the second wireless communication station, a control trailer of the RTS including an indication of an intent to transmit the SU-MIMO transmission to the second wireless communication station; and to transmit the SU-MIMO transmission to the second wireless communication station, upon receipt of a Clear to Send (CTS) from the second wireless communication station indicating that the second wireless communication station is ready to receive the SU-MIMO transmission.

Abstract: A contact arrangement includes a plurality of contact groups. At least one of the contact groups includes a plurality of shared contacts, a plurality of dedicated contacts, and a plurality of ground contacts. The shared contacts in a first mode or a second mode transmit signals corresponding to the first mode or the second mode. The dedicated contacts transmit the signals corresponding to the first mode and do not transmit the signals corresponding to the second mode. The ground contacts surround the shared contacts and the dedicated contacts.

Abstract: A manufacturing method for a memory structure including the following steps is provided. A bit line structure is formed on the substrate. A contact structure is formed on the substrate on one side of the bit line structure. A capacitor structure is formed on the contact structure. The capacitor structure includes a first electrode, a second electrode and an insulating layer. The first electrode is disposed on the contact structure in a misaligned manner. The first electrode includes a first bottom surface and a second bottom surface. The first bottom surface is lower than the second bottom surface. The first bottom surface is disposed on the contact structure. The second electrode is located on the first electrode. The insulating layer is disposed between the first electrode and the second electrode.

Abstract: In a general aspect, a method includes measuring, for a permanent magnet motor having a rotor rotating at a speed, a direct-axis voltage in a rotor frame of reference. The speed is determined by an angular position sensor. The method further includes comparing the measured direct-axis voltage with a reference voltage, and determining, based on the comparing, an angle offset estimate of the angular position sensor. The method also includes iteratively adjusting the angle offset estimate until the measured direct-axis voltage substantially equals the reference voltage.