Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a sacrificial layer over the semiconductor substrate, etching the sacrificial layer to form a sacrificial pattern, etching the semiconductor substrate using the sacrificial pattern as an etching mask to form an active region of the semiconductor substrate, trimming the sacrificial pattern, and replacing the trimmed sacrificial pattern with a gate electrode.

Abstract: A thermometer includes an input unit, a control unit, a temperature sensor and an output unit. In response to an input operation is applied on the input unit, the control unit starts to perform a temperature detecting procedure, wherein the control unit instructs the temperature sensor to periodically perform a plurality of temperature detecting operations to obtain a plurality of detected temperature values corresponding to the temperature detecting operations, and only records X largest valid temperature values among the obtained temperature values. In response to determining that the performed temperature to detecting procedure is completed, the control unit removes the largest one among the recorded valid temperature values and calculates an average value of the remaining one or more target temperature values as a temperature of a target object, so as to instruct the output unit display the temperature.

Abstract: A blood pressure measurement device and a calculation method thereof are disclosed. The blood pressure measurement device includes a pressurizing motor unit and an exhaust valve unit in communication with an airbag unit. The blood pressure calculation method includes steps of controlling the pressurizing motor unit to pressurize the airbag unit; measuring pressurized measurement data from the airbag unit in a pressurization process; controlling the pressurizing motor unit to stop pressurizing the airbag unit, and controlling the exhaust valve unit to depressurize the airbag unit; measuring depressurized measurement data from the airbag unit in a depressurization process; extracting blood pressure parameters from the pressurized measurement data and the depressurized measurement data; calculating an average of the blood pressure parameters extracted from the pressurized measurement data and the depressurized measurement data, to obtain a blood pressure measurement result.

Abstract: A method for manufacturing a semiconductor device includes forming contacts disposed in a dielectric layer. The method of forming the contacts includes forming contact holes and then filling with a conductive material. The method of forming the contact holes includes steps of forming openings in the dielectric layer to expose active regions, introducing a first oxygen plasma and a first fluorine plasma to remove by-products and oxidize inner surfaces of the openings, introducing a second oxygen plasma and a second fluorine plasma to remove the oxidized inner surfaces and repair the active regions, introducing a third oxygen plasma to oxidize inner surfaces again to form an oxide layer, and removing the oxide layer. The cross-sectional structure of two adjacent contact holes includes a capital, a base, and a shaft between the capital and the base, wherein the shaft has a smaller width than the base and the capital.

Abstract: A non-contact body temperature measuring device includes a temperature measuring unit, a Doppler radar, a processing unit, and a display unit. The temperature measuring unit measures a temperature of a human body in a non-contact manner. The Doppler radar emits radar waves to the human body and receives reflected radar waves. The processing unit, which is electrically connected to the temperature measuring unit and the Doppler radar, determines measurement spots on the human body based on the reflected radar waves, controls the temperature measuring unit to measure temperatures of the measurement spots, and generates a body temperature measuring value based on the temperatures of the measurement spots. The display unit is electrically connected to the processing unit for displaying the body temperature measuring value.

Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

Abstract: Disclosed are methods and systems for ranking content. In one aspect, a method of ranking content for display includes identifying, via hardware processing circuitry, interactions by a single account with content pairs, each of the content in the content pairs included in a plurality of content, aggregating, via the hardware processing circuitry, the identified interactions across a plurality of accounts, associating, via the hardware processing circuitry, probabilities with each content in the plurality of content based on the aggregated interactions, ranking, via the hardware processing circuitry, the plurality of content based on the associated probabilities; and selecting, via the hardware processing circuitry, content ranked above a threshold for display.

Abstract: A method includes forming a stack of material layers to cover an array region and a periphery region of a substrate. A first patterned mask layer is formed, and the pattern of the first patterned mask layer is transferred to the stack of material layers, thereby forming a first array pattern and a first periphery pattern respectively in the array and periphery regions. A second patterned mask layer is provided above the first array and periphery patterns. The pattern of the second patterned mask is not aligned with the pattern of the first patterned mask. The pattern of the second patterned mask layer is transferred to form the first and second sacrificial patterns respectively in the array and periphery regions. The first array pattern, the first and second sacrificial patterns, and the first periphery pattern are simultaneously transferred to form a second array pattern and a second periphery pattern.

Abstract: The disclosure provides a method of fabricating a semiconductor device, where the method includes the following operations. A semiconductor stack including a silicon-containing layer, an oxide deposited on a portion of the silicon-containing layer, an underlayer, and a resist layer is formed. The resist layer is patterned to form a first opening in the resist layer. The underlayer is etched to extend the first opening into the underlayer, where a top surface of the oxide is exposed by the first opening. The oxide and the underlayer are etched with a first etchant, where a ratio of etching rates of the oxide and the underlayer is about 1:1. The oxide and the silicon-containing layer are etched with a second etchant to form a second opening below the first opening, where an etching rate of the oxide is higher than that of the silicon-containing layer.

Abstract: A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a substrate, a plurality of first gate structures, a first dielectric layer, a second dielectric layer, a third dielectric layer and a contact plug. The first gate structures are formed on an array region of the substrate. The first dielectric layer is formed on top surfaces and sidewalls of the first gate structures. The second dielectric layer is formed on the first dielectric layer and in direct contact with the first dielectric layer. The second dielectric layer and the first dielectric layer are made of the same material. The third dielectric layer is formed between the first gate structures and defines a plurality of contact holes exposing the substrate. The contact plug fills the contact holes.

Abstract: Some demonstrative embodiments include apparatuses, systems and/or methods of communicating a Single-User (SU) Multiple-Input-Multiple-Output (MIMO) transmission. For example, a first wireless communication station may be configured to transmit a Request to Send (RTS) to a second wireless communication station via a plurality of SU MIMO Transmit (Tx) sectors of the first wireless communication station, the RTS to establish a Transmit Opportunity (TXOP) to transmit an SU-MIMO transmission to the second wireless communication station, a control trailer of the RTS including an indication of an intent to transmit the SU-MIMO transmission to the second wireless communication station; and to transmit the SU-MIMO transmission to the second wireless communication station, upon receipt of a Clear to Send (CTS) from the second wireless communication station indicating that the second wireless communication station is ready to receive the SU-MIMO transmission.

Abstract: A method for forming a semiconductor memory structure includes forming a plurality of conductive wire structures over a semiconductor substrate, and forming a plurality of spacer structures along the sidewalls of the conductive wire structures. Each of the spacer structures includes a first spacer. The method also includes forming a plurality of dielectric strips across the conductive wire structures, forming a plurality of conductive strips over the conductive wire structures and the dielectric strips, performing a patterning process on the conductive strips to form a plurality of conductive pads, and removing the first spacer of each of the spacer structures to form a gap in each of the spacer structures.

Abstract: A memory structure including a substrate, a bit line structure, a contact structure, a stop layer, and a capacitor structure is provided. The substrate includes a memory array region. The bit line structure is located in the memory array region and located on the substrate. The contact structure is located in the memory array region and located on the substrate on one side of the bit line structure. The stop layer is located in the memory array region and located above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. A bottom surface of the capacitor structure is lower than a bottom surface of the stop layer.

Abstract: A memory device includes a substrate, a bit line, a first insulating film, a second insulating film, a third insulating film, and a contact. The bit line is disposed over the substrate. The first insulating film is disposed on a sidewall of the bit line. The second insulating film is disposed on the first insulating film and is made of a different material than the first insulating film. The third insulating film is disposed on the second insulating film and is made of a different material than the second insulating film. The top surfaces of the second insulating film and the third insulating film are lower than the top surface of the first insulating film. The contact is disposed over the substrate and adjacent to the bit line. The width of the lower portion of the contact is less than the width of the upper portion of the contact.

Abstract: A memory structure including a substrate, a bit line structure, a contact structure, a stop layer, and a capacitor structure is provided. The substrate includes a memory array region. The bit line structure is located in the memory array region and located on the substrate. The contact structure is located in the memory array region and located on the substrate on one side of the bit line structure. The stop layer is located in the memory array region and located above the bit line structure. The capacitor structure is located in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. A bottom surface of the capacitor structure is lower than a bottom surface of the stop layer.

Abstract: Provided is a DRAM including: a substrate, a plurality of chop structures, and a plurality of buried word lines. The plurality of chop structures are located in the substrate. Each of the plurality of chop structures comprises a first portion and a second portion. The first portion is located above the second portion, and a width of the second portion is less than a width of the first portion. The plurality of buried word lines, located at bottoms of a plurality of buried word line trenches. The plurality of buried word line trenches passes through the first portion of the plurality of chop structures and the substrate.

Abstract: A nasal mucus suction device includes an air pump and a head structure. The air pump has an intake tube and an outlet tube. The head structure is coupled to the intake tube and the outlet tube of the air pump, and defines a channel between a nasal mucus suction inlet and a gas outlet. The channel includes a first channel section in communication with the nasal mucus suction inlet, and a second channel section in communication with the gas outlet. The first channel section includes at least one mucus storage cavity, the second channel section is in communication with the intake tube and the outlet tube of the air pump. The first channel section has a maximized path length, and includes an anti-backflow channel structure. The second channel section includes a noise reduction space.

Abstract: Disclosed is a double-knit textile having a plurality of texturized inlay yarns movably positioned between a front layer (112) and a back layer (114) of the double-knit textile. The double-knit textile includes areas where a yarn from the back layer is transferred to the front layer and knitted in one or more knit stitches to form an interknitted location (116). The number of interknitted locations per unit area varies in different portions of the double-knit textile. The double-knit textile is configured to provide zoned insulation and/or cushioning features.