Patents by Inventor Paige M. Holm
Paige M. Holm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7378346Abstract: A method is provided for forming a monolithically integrated optical filter, for example, a Fabry-Perot filter, over a substrate (10). The method comprises forming a first mirror (16) over the substrate (10). A plurality of etalon material layers (32, 34, 36, 38) are formed over the mirror (16), and a plurality of etch stop layers (42, 44, 46) are formed, one each between adjacent etalon material layers (32, 34, 36, 38). A photoresist is patterned to create an opening (54) over the top etalon material layer (38) and an etch (56) is performed down to the top etch stop layer (46). An oxygen plasma (58) may be applied to convert the etch stop layer (46) within the opening (54) to silicon dioxide (57). The photoresist patterning, etching, and applying of an oxygen plasma may be repeated as desired to obtain the desired number of levels (82, 84, 86, 88). A second mirror (72) is then formed on each of the levels (82, 84, 86, 88).Type: GrantFiled: March 22, 2006Date of Patent: May 27, 2008Assignee: Motorola, Inc.Inventors: Ngoc V. Le, Jeffrey H. Baker, Diana J. Convey, Paige M. Holm, Steven M. Smith
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Patent number: 6984816Abstract: An exemplary system and method for providing a vertically integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS layer (420); and a photosensing element (380) fabricated in a vertically integrated optically active layer (320, 350), where the optically active layer (320, 350) is bonded to the CMOS layer (420) and the optically active layer (320, 350) is positioned near a metalization surface (405) of the CMOS layer (420). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics.Type: GrantFiled: August 13, 2003Date of Patent: January 10, 2006Assignee: Motorola, Inc.Inventors: Paige M. Holm, Jon J. Candelaria
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Patent number: 6965128Abstract: High quality epitaxial layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy and epitaxial growth of single crystal silicon onto single crystal oxide materials. A microresonator device is formed overlying the monocrystalline substrate.Type: GrantFiled: February 3, 2003Date of Patent: November 15, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Paige M. Holm, Barbara Foley Barenburg, Joyce K. Yamamoto, Fred V. Richard
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Patent number: 6927432Abstract: An exemplary system and method for providing a vertically integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS layer (420); and a photosensing element (380) fabricated in a vertically integrated optically active layer (320, 350), where the optically active layer (320, 350) is bonded to the CMOS layer (420) and the optically active layer (320, 350) is positioned near a metalization surface (405) of the CMOS layer (420). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics.Type: GrantFiled: August 13, 2003Date of Patent: August 9, 2005Assignee: Motorola, Inc.Inventors: Paige M. Holm, Jon J. Candelaria
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Patent number: 6809008Abstract: An exemplary system and method for providing an integrated photosensing element suitably adapted for use in CMOS imaging applications is disclosed as comprising inter alia: a processed CMOS host wafer (460) bonded with a monocrystalline, optically active donor wafer (300); a photosensing element (390) integrated in said optically active donor wafer (300) having an interconnect via (505, 495, 485) substantially decoupled from the photosensing element (390), wherein the host (460) and donor (300) wafers are bonded through the optically active material in a region disposed near a metalization surface (450, 455, 445) of the CMOS layer (460) in order to allow fabrication of the interconnect (505, 495, 485). Disclosed features and specifications may be variously controlled, configured, adapted or otherwise optionally modified to further improve or otherwise optimize photosensing performance or other material characteristics.Type: GrantFiled: August 28, 2003Date of Patent: October 26, 2004Assignee: Motorola, Inc.Inventors: Paige M. Holm, Jon J. Candelaria
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Publication number: 20040150043Abstract: High quality epitaxial layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy and epitaxial growth of single crystal silicon onto single crystal oxide materials. A microresonator device is formed overlying the monocrystalline substrate.Type: ApplicationFiled: February 3, 2003Publication date: August 5, 2004Applicant: MOTOROLA, INC.Inventors: Paige M. Holm, Barbara Foley Barenburg, Joyce K. Yamamoto, Fred V. Richard
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Publication number: 20030218666Abstract: Semiconductor print engine structures (304) are formed by growing high quality epitaxial layers (26) of monocrystalline materials overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. The compliant substrate includes an accommodating buffer layer (24) including a layer of monocrystalline oxide spaced apart from a silicon wafer (22) by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer (24).Type: ApplicationFiled: May 22, 2002Publication date: November 27, 2003Applicant: Thoughtbeam, Inc.Inventors: Paige M. Holm, Fred V. Richard
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Publication number: 20030209811Abstract: A method and apparatus for decreasing contact resistance between a ohmic contact (120) and a semiconductor material (106) are disclosed. Increased contact resistance, which occurs as a result of encroachment of the ohmic contact (120) into the semiconductor material (106) is compensated for by notching edges of the ohmic contact (1210) to increase the effective surface area between abutting surfaces of the ohmic contact (120) and semiconductor material (106).Type: ApplicationFiled: June 16, 2003Publication date: November 13, 2003Inventors: Paige M. Holm, Olin L. Hartin, H. Philip Li
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Patent number: 6596616Abstract: A method and apparatus for decreasing contact resistance between a ohmic contact (120) and a semiconductor material (106) are disclosed. Increased contact resistance, which occurs as a result of encroachment of the ohmic contact (120) into the semiconductor material (106) is compensated for by notching edges of the ohmic contact (1210) to increase the effective surface area between abutting surfaces of the ohmic contact (120) and semiconductor material (106). The increase in surface area increases the effective transfer length of the contact, which correspondingly reduces contact resistance and improves device performance.Type: GrantFiled: April 19, 2002Date of Patent: July 22, 2003Assignee: Motorola, Inc.Inventors: Paige M. Holm, Olin L. Hartin, H. Philip Li
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Publication number: 20030035964Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.Type: ApplicationFiled: August 16, 2001Publication date: February 20, 2003Applicant: Motorola, Inc.Inventors: Fred Richard, Paige M. Holm
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Publication number: 20030036217Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The foregoing is utilized for a microcavity semiconductor laser coupled to a waveguide.Type: ApplicationFiled: November 6, 2001Publication date: February 20, 2003Applicant: MOTOROLA, INC.Inventors: Fred V. Richard, Paige M. Holm
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Publication number: 20030030062Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.Type: ApplicationFiled: August 9, 2001Publication date: February 13, 2003Applicant: MOTOROLA, INC.Inventors: Paige M. Holm, Barbara Foley Barenburg, Fred Richard, Joyce Yamamoto
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Publication number: 20030020104Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.Type: ApplicationFiled: July 25, 2001Publication date: January 30, 2003Applicant: MOTOROLA, INC.Inventors: Albert A. Talin, Alexander A. Demkov, Paige M. Holm
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Publication number: 20030016895Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.Type: ApplicationFiled: July 23, 2001Publication date: January 23, 2003Applicant: MOTOROLA, INC.Inventors: Paige M. Holm, Kurt W. Eisenbeiser, Joyce Yamamoto
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Publication number: 20030017626Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.Type: ApplicationFiled: July 23, 2001Publication date: January 23, 2003Applicant: MOTOROLA INC.Inventors: Lyndee L. Hilt, Jay A. Curless, Paige M. Holm
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Publication number: 20030006470Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. A thermo-electric device is integrated into the semiconductor structure.Type: ApplicationFiled: July 5, 2001Publication date: January 9, 2003Applicant: MOTOROLA, INC.Inventors: Steven James Franson, Daniel S. Marshall, Paige M. Holm, John E. Holmes, Bruce Allen Bosco, Rudy M. Emrick
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Patent number: 5940683Abstract: A light emitting diode display package and method of fabricating a light emitting diode (LED) display package including a LED array display chip, fabricated of an array of LEDs, formed on a substrate, having connection pads positioned about the perimeter of the LED array display chip, a separate silicon driver chip having connection pads routed to an uppermost surface, positioned to cooperatively engage those of the display chip when properly registered and interconnected using wafer level processing technology. The display chip being flip chip mounted to the driver chip and having a layer of interchip bonding dielectric positioned between the space defined by the display chip and the driver chip. The LED display and driver chip package subsequently having selectively removed the substrate onto which the LED array was initially formed, thereby exposing the connection pads of the display chip and a remaining indium-gallium-aluminum-phosphide (InGaAlP) epilayer.Type: GrantFiled: January 18, 1996Date of Patent: August 17, 1999Assignee: Motorola, Inc.Inventors: Paige M. Holm, Chan-Long Shieh, Curtis D. Moyer
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Patent number: 5893721Abstract: A method of fabricating an active matrix LED array includes forming layers of material on a substrate, which layers cooperate to emit light when activated. Row and column dividers are formed in the layers to divide the layers into an array of LEDs arranged in rows and columns. One FET is formed on the row dividers in association with each LED and a source of each FET is connected to an anode of the associated LED. Row and column buses are formed on the row and column dividers, respectively, and the drain of each FET is connected to an adjacent row bus with the gate of each FET being connected to an adjacent column bus. A cathode for each LED is connected as a common terminal for all of the LEDs in the array.Type: GrantFiled: March 24, 1997Date of Patent: April 13, 1999Assignee: Motorola, Inc.Inventors: Rong-Ting Huang, Phil Wright, Paige M. Holm
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Patent number: 5866922Abstract: An integrated matrix of light emitting devices includes a plurality of isolated semiconductor LEDs positioned in a matrix of rows and columns on the surface of a substrate. A plurality of column buses, one each positioned adjacent each column of semiconductor LEDs, is provided with each of the column buses being connected to a first terminal of each semiconductor LED in the adjacent column of semiconductor LEDs and each of the column buses providing an exposed planar surface. A plurality of OEDs is positioned on the exposed planar surface of each column bus with a first terminal of each OED connected to the column bus.Type: GrantFiled: December 23, 1996Date of Patent: February 2, 1999Assignee: Motorola, Inc.Inventors: Rong Ting Huang, Phil Wright, Paige M. Holm, Song Q. Shi
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Patent number: 5827753Abstract: A method of fabricating a monolithically integrated LED array and driving circuitry includes sequentially forming overlying layers of material on the surface of a semiconductor substrate, the layers cooperating to emit light when activated. An insulating layer is formed on the layers and the layers are isolated into an array area and driver circuitry areas with row and column dividers dividing the array area into an array of LEDs arranged in rows and columns. Row and column driver circuits are formed on the insulating layer in the driver circuitry areas and row and column buses individually couple each LED in the array to row and column driver circuits.Type: GrantFiled: March 20, 1997Date of Patent: October 27, 1998Assignee: Motorola, Inc.Inventors: Rong-Ting Huang, Phil Wright, Chan-Long Shieh, Paige M. Holm