Patents by Inventor Paolo Ferraris

Paolo Ferraris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6109106
    Abstract: A movable mass forming a seismic mass is formed starting from an epitaxial layer and is covered by a weighting region of tungsten which has high density. To manufacture the mass, buried conductive regions are formed in the substrate. Then, at the same time, a sacrificial region is formed in the zone where the movable mass is to be formed and oxide insulating regions are formed on the buried conductive regions so as to partially cover them. An epitaxial layer is then grown, using a nucleus region. A tungsten layer is deposited and defined and, using a silicon carbide layer as mask, the suspended structure is defined. Finally, the sacrificial region is removed, forming an air gap.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: August 29, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventors: Paolo Ferrari, Benedetto Vigna, Pietro Montanini, Marco Ferrera
  • Patent number: 6104073
    Abstract: The acceleration sensor is formed in a monocrystalline silicon wafer forming part of a dedicated SOI substrate presenting a first and second monocrystalline silicon wafer separated by an insulting layer having an air gap. A well is formed in the second wafer over the air gap and is subsequently trenched up to the air gap to release the monocrystalline silicon mass forming the movable mass of the sensor; the movable mass has two numbers of movable electrodes facing respective pluralities of fixed electrodes. In the idle condition, each movable electrode is separated by different distances from the two fixed electrodes facing the movable electrode.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: August 15, 2000
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Paolo Ferrari, Mario Foroni, Benedetto Vigna, Flavio Villa
  • Patent number: 6090638
    Abstract: A sensor having high sensitivity is formed using a suspended structure with a high-density tungsten core. To manufacture it, a sacrificial layer of silicon oxide, a polycrystal silicon layer, a tungsten layer and a silicon carbide layer are deposited in succession over a single crystal silicon body. The suspended structure is defined by selectively removing the silicon carbide, tungsten and polycrystal silicon layers. Then spacers of silicon carbide are formed which cover the uncovered ends of the tungsten layer, and the sacrificial layer is then removed.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: July 18, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventors: Benedetto Vigna, Paolo Ferrari, Marco Ferrera, Pietro Montanini
  • Patent number: 6071021
    Abstract: The present invention relates to an apparatus for developing and digitizing an image-wise exposed silver halide radiographic film comprising: an automatic radiographic film processing unit having an output, wherein the processing unit develops the image-wise exposed silver halide radiographic film to create a visible image on the radiographic film; a radiographic film digitizer having an input, wherein the radiographic film digitizer is vertically positioned in relation to a lateral side of the radiographic film processing unit, and photoelectrically reads the visible image on the radiographic film; and an integrated docking unit having a connecting means which connects the radiographic film processing unit to the film digitizer and transports the radiographic film from the output of the radiographic film processing unit to the radiographic film digitizer. A method for the automatic processing and digitizing of an image-wise exposed radiographic film is also described.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: June 6, 2000
    Assignee: Eastman Kodak Company
    Inventors: Andrea Gagliardo, Paolo Ferraris, Bernardo Cerisola
  • Patent number: 6072665
    Abstract: A suspension arm (125) for a head (120) of a disk storage device comprises at least one wall (225, 230) substantially perpendicular to the disk (105) and having a portion (238, 239) which is deformable parallel to a plane extending through a longitudinal axis (235) of the suspension arm (125) and perpendicular to the at least one wall (225, 230), and piezoelectric member (240, 255) which can deform the portion (238, 239) in order correspondingly to move the head (120), the piezoelectric member (240-255) being fixed to the portion (238, 239) of the at least one wall (225, 230).
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: June 6, 2000
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Paolo Ferrari, Bruno Murari, Benedetto Vigna
  • Patent number: 6051854
    Abstract: An integrated semiconductor device comprises, reciprocally superimposed, a thermally insulating region; a thermal conduction region of a high thermal conductivity material; a passivation oxide layer; and a gas sensitive element. The thermal conduction region defines a preferential path towards the gas sensitive element for the heat generated by the heater element, thereby the heat dispersed towards the substrate is negligible during the operation of the device.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: April 18, 2000
    Assignee: STMicroelectronics S.r.l.
    Inventors: Benedetto Vigna, Paolo Ferrari, Ubaldo Mastromatteo
  • Patent number: 6003374
    Abstract: An acceleration sensor is described which is formed by planar technology on a substrate. It includes a core of ferromagnetic material and, coupled conductively together by the core, a first winding adapted to be connected to a power supply and a second winding adapted to be connected to circuit means for measuring an electrical magnitude induced therein. The core has two suspended portions which are free to bend as a result of an inertial force due to an accelerative movement of the sensor itself. The bending causes lengthening of the core and hence a variation in the reluctance of the magnetic circuit. If a constant current is supplied to the first winding, a voltage is induced in the second winding as a result of the variation in the magnetic flux caused by the variation in reluctance.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: December 21, 1999
    Assignee: SGS-Thomson Microelectronics S.R.L.
    Inventors: Benedetto Vigna, Paolo Ferrari, Ubaldo Mastromatteo
  • Patent number: 5942783
    Abstract: A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semiconductor layer, an output terminal, and a supply terminal. A barrier well is formed in the semiconductor layer and adjacent to at least a portion of the periphery of the monolithic output stage. The barrier well extends to the surface of the semiconductor layer and has a first conductivity. A diode having first and second diode regions is disposed in the semiconductor layer. The first diode region is coupled to the supply terminal. The diode is operable to prevent current flow from the barrier well to the supply terminal when the voltage between the supply and output terminals has a first polarity.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: August 24, 1999
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Davide Brambilla, Edoardo Botti, Paolo Ferrari
  • Patent number: 5883009
    Abstract: The chemoresistive gas sensor comprises a heating element integrated in a dedicated SOI substrate having an air gap in the intermediate oxide layer between two wafers of monocrystalline silicon. A sensitive element of tin oxide is formed over the heating element and separated from it by a dielectric insulating and protective layer. A trench formed at the end of the fabrication of the device, extends from the surface of the wafer in which the heating element is integrated, up to the air gap to mechanically separate and insulate the sensitive element from the rest of the chip, thereby improving the mechanical characteristics sensitivity and response of the sensor.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: March 16, 1999
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Flavio Villa, Paolo Ferrari, Benedetto Vigna
  • Patent number: 5756387
    Abstract: Zener diode with high stability in time and low noise for integrated circuits and provided in an epitaxial pocket insulated from the rest of a type N epitaxial layer grown on a substrate of type P semiconductor material.In said pocket are included a type N+ cathode region and a type P anode region enclosing it.The cathode region has a peripheral part surrounding a central part extending in the anode region less deeply than the peripheral part.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: May 26, 1998
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Flavio Villa, Paolo Ferrari
  • Patent number: 5515224
    Abstract: A transistor in an output stage has an emitter connected to a supply rail and a collector connected to an output node. The transistor is protected against the effects of accidental shortcircuiting of the output node of the output stage with a positive pole of a battery while the circuit is unpowered, by a protection transistor of the same type as the transistor to be protected. The protection transistor has an emitter connected to the base of the output transistor, a collector connected to the output node of the output stage, and a base connected through a biasing resistance to the supply rail on the output stage. The protection transistor and an interdigitated structure of the transistor may be formed within the same pocket, thus reducing the required area.
    Type: Grant
    Filed: February 7, 1994
    Date of Patent: May 7, 1996
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Edoardo Botti, Andrea Fassina, Paolo Ferrari
  • Patent number: 5185649
    Abstract: A circuital arrangement which comprises a vertical PNP transistor with insulated collector, which has a P-type collector structure surrounded by an N-type well and forms a junction therewith.
    Type: Grant
    Filed: March 26, 1991
    Date of Patent: February 9, 1993
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Franco Bertotti, Paolo Ferrari
  • Patent number: 5021860
    Abstract: The device for shielding the electrons injected towards the substrate by an epitaxial pocket which reaches a negative voltage with respect to said substrate, comprises a debiasing transistor arranged in reverse configuration (with collector and emitter swapped) in the same epitaxial pocket reaching a negative voltage. The transistor is connected with its emitter and its collector between the buried layer of the pocket reaching a negative voltage and the substrate, so as to debias the junction formed by the buried layer and the substrate.
    Type: Grant
    Filed: October 11, 1988
    Date of Patent: June 4, 1991
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Franco Bertotti, Paolo Ferrari, Maria T. Gatti
  • Patent number: 4935796
    Abstract: A device for minimizing parasitic junction capacitances in an isolated collector vertical PNP transistor, having a terminal N connected to an epitaxial n layer, comprises a bootstrap circuit including an emitter follower vertical PNP transistor having its emitter and base respectively connected to the terminal of the epitaxial n layer and the collector of the isolated collector transistor; further, a bias resistance is connected between the emitter and one pole of a voltage supply to the emitter follower.
    Type: Grant
    Filed: February 8, 1988
    Date of Patent: June 19, 1990
    Assignee: SGS-Thomson Microelectronics S. R. L.
    Inventors: Maurizio Zuffada, Fabrizio Sacchi, Paolo Ferrari
  • Patent number: 4910159
    Abstract: The collector area of a lateral PNP transistor may be incrementally increased during an electic testing step on wafer of an integrated circuit by purposely forming an auxiliary p-type diffused collector region having fractional dimensions near the primary collector region of the transistor and by permanently shorcircuiting the two regions by means of a "Zener zapping" technique, by forcing a current through the inversely biased base-collector junction utilizing a suitable contact pad connected to the auxiliary collector region to create localized power dissipation conditions sufficient to melt the metal of the respective metal at the adjacent contacts and to form a permanent connection between the two metals. The technique is very useful for adjusting the value of the output current(s) in precision current generating circuits.
    Type: Grant
    Filed: December 22, 1988
    Date of Patent: March 20, 1990
    Assignee: SGS-Thomson Microelectronics, s.r.l
    Inventors: Franco Bertotti, Paolo Ferrari, Mario Foroni, Maria T. Gatti
  • Patent number: 4890149
    Abstract: This integrated device for shielding injected charges in driving circuits for inductive and/or capacitive loads comprises four integrated structures including a first barrier region with high resistivity which surrounds the buried layer of the epitaxial flyback pocket which may be set at a potential lower than ground on the side of the buried layer which faces the driving circuit pocket; a first charge collecting region provided in the epitaxial flyback pocket; a third low-loss diode structure, formed in an epitaxial pocket which is isolated from the flyback pocket and is arranged between the latter and the driving circuit, and connected so as to clamp the voltage between the epitaxial flyback pocket and the substrate to the diode direct conduction voltage; and, finally, a last barrier structure formed by a charge collecting region connected to the supply voltage.
    Type: Grant
    Filed: September 21, 1987
    Date of Patent: December 26, 1989
    Assignee: SGS Microelettronica Spa
    Inventors: Franco Bertotti, Paolo Ferrari, Maria T. Gatti
  • Patent number: 4887141
    Abstract: The structure of a vertical PNP transistor with isolated collector is modified by forming a P-type diffusion outside the perimeter of a sinker collector diffusion to form an auxiliary collector capable of detecting the injection of current toward the substrate when the integrated transistor saturates. The current gathered by said auxiliary collector is used for activating a saturation limiting circuit formed by an NPN transistor which is switched-on when said said current gathered by said auxiliary collector reaches a threshold value and which in turn switches-on a PNP transistor having an emitter and a collector connected respectively to the emitter and to the base of the PNP vertical transistor with isolated collector for reducing the driving base current thereto.
    Type: Grant
    Filed: October 19, 1988
    Date of Patent: December 12, 1989
    Assignee: SGS-Thomson Microelectronics s.r.l.
    Inventors: Franco Bertotti, Paolo Ferrari, Maria T. Gatti
  • Patent number: 4829344
    Abstract: This electronic semiconductor device for protecting integrated circuits against electrostatic discharges has a minimal bulk, can withstand high damaging voltages and be produced during the same production phases as the integrated circuit to be protected. The device comprises a pair of diodes connected back to back, arranged between an input of the integrated circuit to be protected and the ground line, with the cathodes connected together and formed by a single semiconductor layer and the anodes formed in a single process phase by employing top-bottom production techniques.
    Type: Grant
    Filed: October 20, 1986
    Date of Patent: May 9, 1989
    Assignee: SGS Microelettronica SPA
    Inventors: Franco Bertotti, Paolo Ferrari
  • Patent number: D320461
    Type: Grant
    Filed: October 23, 1989
    Date of Patent: October 1, 1991
    Assignee: Flos S.p.A.
    Inventors: Luciano Pagani, Angelo Perversi, Paolo Ferrari
  • Patent number: RE35486
    Abstract: A circuital arrangement which comprises a vertical PNP transistor with insulated collector, which has a P-type collector structure surrounded by an N-type well and forms a junction therewith.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: April 1, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Franco Bertotti, Paolo Ferrari