Patents by Inventor Paolo Ferraris

Paolo Ferraris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4740821
    Abstract: Described is an improved NPN equivalent structure with a breakdown voltage higher than the intrinsic breakdown voltage of the NPN transistor utilizing a complementary PNP transistor and a JFET transistor with the gate connected to ground, the drain connected to the base of the PNP and the source connected to the collectors of the complementary pair. An integrated form of the structure is particularly advantageous and the equivalent NPN transistor is substantially exempt from Early effect and has improved output current capacity.
    Type: Grant
    Filed: March 5, 1987
    Date of Patent: April 26, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Franco Bertotti, Maurizio Zuffada, Paolo Ferrari
  • Patent number: 4739378
    Abstract: Described is an integrated semiconductor structure for the protection from electrical discharges of electrostatic origin of particularly sensitive components of an integrated circuit. The structure is almost entirely formed directly underneath a particular input pad thus requiring a minimum useful area and is characterized by very high damaging voltage and speed of intervention because of the extremely low series resistance of the two zener junctions constituting the structure.
    Type: Grant
    Filed: February 17, 1987
    Date of Patent: April 19, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Paolo Ferrari, Franco Bertotti
  • Patent number: 4725810
    Abstract: This method of making an implanted resistor comprises the steps of implanting the resistor with ordinary techniques and deposition over the implanted resistor of a polysilicon layer having a set thickness and fully covering the resistor. Thus, the resulting resistor is unaffected by any subsequent thermal treatments and its value remains constant irrespective of any high potential metal layers or connections crossing it. The method affords in particular resistive values of the order of 1 kOhms/square.
    Type: Grant
    Filed: June 20, 1986
    Date of Patent: February 16, 1988
    Assignee: SGS Microelettronica S.p.A.
    Inventors: Mario Foroni, Paolo Ferrari, Franco Bertotti
  • Patent number: 4663647
    Abstract: A buried-resistance semiconductor device is constructed by forming a P-type monocrystalline silicon substrate on which an epitaxial layer of silicon doped with type N impurities is grown, a portion of the epitaxial layer being insulated by a P-type insulating region extending from the substrate to the surface of the epitaxial layer. Two suitably-spaced terminals are secured to the surface of the epitaxial layer in the area bounded by the insulating region. Two separation regions extending into the surface layer are formed in the part of the epitaxial layer between the terminals, and a buried region extends from the substrate between the separation regions without being in contact with them. The three regions are of P-type material, and have an elongated shape and are bounded at the ends by the insulating region.
    Type: Grant
    Filed: September 23, 1985
    Date of Patent: May 5, 1987
    Assignee: SGS Microelettronica SpA
    Inventors: Franco Bertotti, Paolo Ferrari, Luigi Silvestri, Flavio Villa
  • Patent number: 4614962
    Abstract: This controlled electronic switching device for the suppression of transients can change over from a non-conductive state to a conductive state at lower triggering current levels than conventional devices while retaining unaltered its response characteristics to variations in the voltage applied thereacross. The device comprises a main switch which is triggered by a parallel-connected auxiliary switch having smaller junction areas and a higher capacitive current shunt resistance (resistance between base and emitter) than the main switch, thereby it turns on at lower control currents from the gate electrode for a given response to voltage variations.
    Type: Grant
    Filed: December 3, 1984
    Date of Patent: September 30, 1986
    Assignee: SGS-ATES Componenti Elettronici S.p.A.
    Inventors: Franco Bertotti, Paolo Ferrari, Mario Foroni, Sergio Garue
  • Patent number: D273211
    Type: Grant
    Filed: October 26, 1981
    Date of Patent: March 27, 1984
    Assignee: Zether Limited
    Inventor: Paolo Ferrari