Patents by Inventor Parthasarathy Ranganathan

Parthasarathy Ranganathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9778747
    Abstract: Embodiments of the present invention disclose a multimodal and gestural control system. According to one embodiment, the multimodal and gestural control system is configured to detect a gesture command from a user via at least one device of a plurality of devices. A control operation and a destination device are both determined based on the gesture command such that the determined control operation is executed on the determined destination device.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: October 3, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chandra Praphul, Parthasarathy Ranganathan, Sriganesh Madhvanath
  • Patent number: 9767070
    Abstract: One embodiment is a storage system having one or more compute blades to generate and use data and one or more memory blades to generate a computational result. The computational result is generated by a computational function that transforms the data generated and used by the one or more compute blades. One or more storage devices are in communication with and remotely located from the one or more compute blades. The one or more storage devices store and serve the data for the one or more compute blades.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: September 19, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jichuan Chang, Kevin T Lim, Parthasarathy Ranganathan
  • Patent number: 9710335
    Abstract: According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: July 18, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Doe Hyun Yoon, Terence P. Kelly, Jichuan Chang, Naveen Muralimanohar, Robert Schreiber, Parthasarathy Ranganathan
  • Publication number: 20170153977
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for caching data not frequently accessed. One of the methods includes receiving a request for data from a component of a device, determining that the data satisfies an infrequency condition, in response to determining that the data satisfies the infrequency condition: determining a target cache level which defines a cache level within a cache level hierarchy of a particular cache at which to store infrequently accessed data, the target cache level being lower than a highest cache level in the cache level hierarchy, requesting and receiving the data from a memory that is not a cache of the device, and storing the data in a level of the particular cache that is at or below the target cache level in the cache level hierarchy, and providing the data to the component.
    Type: Application
    Filed: February 10, 2017
    Publication date: June 1, 2017
    Inventors: Richard Yoo, Liqun Cheng, Benjamin C. Serebrin, Parthasarathy Ranganathan, Rama Krishna Govindaraju
  • Publication number: 20170109082
    Abstract: An example method includes during execution of a software application by a processor, receiving, by a copy processor separate from the processor, a request for an asynchronous data copy operation to copy data within a memory accessible by the copy processor, wherein the request is received from a copy manager accessible by the software application in a user space of an operating system managing execution of the software application; in response to the request, initiating, by the copy processor, the asynchronous data copy operation; continuing execution of the software application by the processor; determining, by the copy processor, that the asynchronous data copy operation has completed; and in response to determining that the asynchronous copy operation has completed, selectively notifying, by the copy processor, the software application that the asynchronous copy operation has completed.
    Type: Application
    Filed: October 16, 2015
    Publication date: April 20, 2017
    Inventors: Rama Krishna Govindaraju, Liqun Cheng, Parthasarathy Ranganathan, Michael R. Marty, Andrew Gallatin
  • Patent number: 9600417
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for caching data not frequently accessed. One of the methods includes receiving a request for data from a component of a device, determining that the data satisfies an infrequency condition, in response to determining that the data satisfies the infrequency condition: determining a target cache level which defines a cache level within a cache level hierarchy of a particular cache at which to store infrequently accessed data, the target cache level being lower than a highest cache level in the cache level hierarchy, requesting and receiving the data from a memory that is not a cache of the device, and storing the data in a level of the particular cache that is at or below the target cache level in the cache level hierarchy, and providing the data to the component.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: March 21, 2017
    Assignee: Google Inc.
    Inventors: Richard Yoo, Liqun Cheng, Benjamin C. Serebrin, Parthasarathy Ranganathan, Rama Krishna Govindaraju
  • Patent number: 9594687
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for pre-fetching content. One of the systems includes a pre-fetcher configured to perform operations including determining, for a virtual machine executing on a device and using a first virtual machine physical address associated with the virtual machine, a second virtual machine physical address for data to pre-fetch for the execution of the virtual machine on the device, determining, using the second virtual machine physical address and an address mapping that associates virtual machine physical addresses for the virtual machine with device physical addresses for the device, a device physical address for the data, and requesting the data from a memory using the device physical address.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: March 14, 2017
    Assignee: Google Inc.
    Inventors: Richard Yoo, Liqun Cheng, Parthasarathy Ranganathan, Rama Krishna Govindaraju
  • Patent number: 9575889
    Abstract: A memory server providing remote memory for servers independent from the memory server. The memory server includes memory modules and a page table. A memory controller for the memory server allocates memory in the memory modules for each of the servers and manages remote memory accesses for the servers. The page table includes entries identifying the memory module and locations in the memory module storing data for the servers.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: February 21, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jichuan Chang, Parthasarathy Ranganathan, Kevin T. Lim
  • Patent number: 9514044
    Abstract: Disclosed herein are a computing system, integrated circuit, and method to enhance retrieval of cached data. A tracking table is used to initiate a search for data from a location specified in the table, if the data is not in a first level of a multi-level cache hierarchy.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: December 6, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jichuan Chang, Doe Hyun Yoon, Parthasarathy Ranganathan
  • Publication number: 20160342351
    Abstract: A technique includes acquiring a plurality of write requests from at least one memory controller and logging information associated with the plurality of write requests in persistent storage. The technique includes applying the plurality of write requests atomically as a group to persistent storage.
    Type: Application
    Filed: January 23, 2014
    Publication date: November 24, 2016
    Inventors: Sheng Li, Jishen Zhao, Jichuan Chang, Parthasarathy Ranganathan, Alistair Veitch, Kevin T. Lim, Mark Lillibridge
  • Publication number: 20160321176
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for caching data not frequently accessed. One of the methods includes receiving a request for data from a component of a device, determining that the data satisfies an infrequency condition, in response to determining that the data satisfies the infrequency condition: determining a target cache level which defines a cache level within a cache level hierarchy of a particular cache at which to store infrequently accessed data, the target cache level being lower than a highest cache level in the cache level hierarchy, requesting and receiving the data from a memory that is not a cache of the device, and storing the data in a level of the particular cache that is at or below the target cache level in the cache level hierarchy, and providing the data to the component.
    Type: Application
    Filed: April 29, 2015
    Publication date: November 3, 2016
    Inventors: Richard Yoo, Liqun Cheng, Benjamin C. Serebrin, Parthasarathy Ranganathan, Rama Krishna Govindaraju
  • Publication number: 20160306743
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for pre-fetching content. One of the systems includes a pre-fetcher configured to perform operations including determining, for a virtual machine executing on a device and using a first virtual machine physical address associated with the virtual machine, a second virtual machine physical address for data to pre-fetch for the execution of the virtual machine on the device, determining, using the second virtual machine physical address and an address mapping that associates virtual machine physical addresses for the virtual machine with device physical addresses for the device, a device physical address for the data, and requesting the data from a memory using the device physical address.
    Type: Application
    Filed: April 14, 2015
    Publication date: October 20, 2016
    Inventors: Richard Yoo, Liqun Cheng, Parthasarathy Ranganathan, Rama Krishna Govindaraju
  • Publication number: 20160275014
    Abstract: According to an example, a processor generates a memory access request and sends the memory access request to a memory module. The processor receives data from the memory module in response to the memory access request when a memory device in the memory module for the memory access request is busy and unable to execute the memory access request.
    Type: Application
    Filed: October 31, 2013
    Publication date: September 22, 2016
    Inventors: Kevin T. Lim, Sheng Li, Parthasarathy Ranganathan, William C. Hallowell
  • Publication number: 20160267015
    Abstract: A method for mapping virtual memory pages to physical memory pages is described. The method includes receiving a mapping of a virtual memory page to multiple physical memory pages, detecting a request for a transaction to be performed on data contained in the multiple physical memory pages, in which the transaction includes a number of data updates, determining which of the number of multiple physical memory pages contains a latest version of the data to be updated by the transaction, updating a physical memory page by performing the transaction within a physical memory page among the multiple physical memory pages that does not contain the latest version of the data, and updating an indication of which of the physical memory pages contains the latest version of the data pertaining to the transaction.
    Type: Application
    Filed: October 29, 2013
    Publication date: September 15, 2016
    Inventors: Sheng Li, Jishen Zhao, Jichuan Chang, Parthasarathy Ranganathan, Alistair Veitch, Kevin T. Lim
  • Publication number: 20160253105
    Abstract: A method for compressing and compacting memory on a memory device is described. The method includes organizing a number of compressed memory pages referenced in a number of compaction table entries based on a size of the number of compressed memory pages and compressing the number of compaction table entries, in which a compaction table entry comprise a number of fields.
    Type: Application
    Filed: October 31, 2013
    Publication date: September 1, 2016
    Inventors: Jichuan Chang, Sheng Li, Parthasarathy Ranganathan
  • Publication number: 20160239685
    Abstract: According to an example, a hybrid secure non-volatile main memory (HSNVMM) may include a non-volatile memory (NVM) to store a non-working set of memory data in an encrypted format, and a dynamic random-access memory (DRAM) buffer to store a working set of memory data in a decrypted format. A cryptographic engine may selectively encrypt and decrypt memory pages in the working and non-working sets of memory data. A security controller may control memory data placement and replacement in the NVM and the DRAM buffer based on memory data characteristics that include clean memory pages, dirty memory pages, working set memory pages, and non-working set memory pages. The security controller may further provide incremental encryption and decryption instructions to the cryptographic engine based on the memory data characteristics.
    Type: Application
    Filed: July 31, 2013
    Publication date: August 18, 2016
    Inventors: Sheng Li, Jichuan Chang, Parthasarathy Ranganathan, Doe Hyun Yoon
  • Patent number: 9395786
    Abstract: A method for cross-layer power management in a multi-layer system includes determining whether there is a service level violation for an application running on a hardware platform. Power consumption of the hardware platform is controlled in response to the service level violation.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: July 19, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vanish Talwar, Jeffrey S. Autor, Sanjay Kumar, Parthasarathy Ranganathan
  • Patent number: 9348527
    Abstract: Storing data in persistent hybrid memory includes promoting a memory block from non-volatile memory to a cache based on a usage of said memory block according to a promotion policy, tracking modifications to the memory block while in the cache, and writing the memory block back into the non-volatile memory after the memory block is modified in the cache based on a writing policy that keeps a number of the memory blocks that are modified at or below a number threshold while maintaining the memory block in the cache.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: May 24, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jichuan Chang, Parthasarathy Ranganathan
  • Publication number: 20160117196
    Abstract: Log analysis can include transferring compiled log analysis code, executing log analysis code, and performing a log analysis on the executed log analysis code.
    Type: Application
    Filed: July 31, 2013
    Publication date: April 28, 2016
    Inventors: Vanish Talwar, Indrajit Roy, Kevin T. Lim, Jichuan Chang, Parthasarathy Ranganathan
  • Publication number: 20160077922
    Abstract: According to an example, versioned memory implementation may include comparing a global memory version to a block memory version. The global memory version may correspond to a plurality of memory blocks, and the block memory version may correspond to one of the plurality of memory blocks. A subblock-bit-vector (SBV) corresponding to a plurality of subblocks of the one of the plurality of memory blocks may be evaluated. Based on the comparison and the evaluation, a determination may be made as to which level in a cell of one of the plurality of subblocks of the one of the plurality of memory blocks checkpoint data is stored.
    Type: Application
    Filed: July 31, 2013
    Publication date: March 17, 2016
    Inventors: Doe Hyun Yoon, Terence P. Kelly, Jichuan Chang, Naveen Muralimanohar, Robert Schreiber, Parthasarathy Ranganathan