Patents by Inventor Parthasarathy Ranganathan

Parthasarathy Ranganathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8516271
    Abstract: Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: August 20, 2013
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Paolo Faraboschi, Parthasarathy Ranganathan, Naveen Muralimanohar
  • Patent number: 8499116
    Abstract: In a method of managing wear on a plurality of independent storage devices having respective sets of memory cells, access characteristics of the memory cells in the plurality of independent storage devices are monitored. In addition, an instruction to access data on at least one of the memory cells is received and an independent storage device of the plurality of independent storage devices is selected to access data on at least one of the memory cells of the selected independent storage device based upon one or more predetermined selection policies and the monitored access characteristics of the memory cells in the plurality of independent storage devices. Moreover, the selected independent storage device is assigned to access data on at least one of the memory cells of the selected independent storage device according to the received instruction.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: July 30, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David Andrew Roberts, Jichuan Chang, Parthasarathy Ranganathan
  • Patent number: 8472808
    Abstract: This disclosure is directed to optical data path systems that enable unidirectional and bidirectional transmission of optical signals between nodes of a multi-node system such as a multiprocessor system. In one aspect, an optical data path system includes an optical device layer connected to nodes of a multi-node system and a controller. The optical device layer includes a waveguide network of waveguide branches optically connecting each node of the multi-node system to every other node of the multi-node system, resonators disposed adjacent to the waveguide branches, and detectors disposed adjacent to waveguide branches of the waveguide network. Each detector is electronically connected to a node of the multi-node system. The resonators are operated by the controller to control the path of optical signals sent between the nodes of the multi-node system.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: June 25, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David A. Roberts, Jichuan Chang, Parthasarathy Ranganathan
  • Patent number: 8457121
    Abstract: A heterogeneous network switch system includes heterogeneous network switches having a first network switch having a first functionality and a second network switch having a second functionality, where the first functionality differs from the second functionality. In addition, the first network switch and the second network switch are configured to forward data to at least one common server. The system also includes a controller configured to receive data from at least one client and to select one of the first network switch and the second network switch to employ in forwarding the data from the at least one client to the at least one common network equipment.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: June 4, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Puneet Sharma, Sujata Banerjee, Parthasarathy Ranganathan
  • Publication number: 20130111249
    Abstract: The present disclosure includes accessing a local storage device using an auxiliary processor An example computing device (100, 202, 303) includes a local storage device (110, 210, 310), a first processor (112, 212, 312) able to access the local storage device (110, 210, 310), an auxiliary processor (114, 220, 360) able to access the local storage device (110, 210, 310) while the first processor (112, 212, 312) is shut down, wherein the auxiliary processor (114, 220, 360) uses less power than the first processor (112, 212, 312), and a management agent (125, 225, 370) to initiate an accessing of the local storage device (110, 210, 310) by the auxiliary processor (114, 220, 360) if a load associated with the computing device (100, 202, 303) falls below a particular threshold. One of the first processor (112, 212, 312) and the auxiliary processor (114, 220, 360) is able to access the local storage device (110, 210, 310) at a time.
    Type: Application
    Filed: July 21, 2010
    Publication date: May 2, 2013
    Inventors: Jichuan Chang, Parthasarathy Ranganathan, Mehul A. Shah
  • Publication number: 20130111107
    Abstract: A tier identification (TID) is to indicate a characteristic of a memory region associated with a virtual address in a tiered memory system. A thread may be serviced according to a first path based on the TID indicating a first characteristic. The thread may be serviced according to a second path based on the TID indicating a second characteristic.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 2, 2013
    Inventors: Jichuan Chang, Kevin T. Lim, Parthasarathy Ranganathan
  • Publication number: 20130094138
    Abstract: Example computer racks to improve environmental sustainability in data centers are disclosed. An example computer rack includes a spine (125); a first set of support structures (500) and a second set of support structures (500) extending from the spine (125). Each of the support structures (500) is positioned to receive a respective blade. A first communication port is carried by the spine (125) and associated with the first set of support structures (500). A second communication port is carried by the spine (125) and associated with the second set of support structures (500).
    Type: Application
    Filed: June 16, 2010
    Publication date: April 18, 2013
    Inventors: Justion James Meza, Jichuan Chang, Parthasarathy Ranganathan, Amip J. Shah, Cullen E. Bash, Chih C. Shih
  • Patent number: 8392737
    Abstract: A system for controlling power consumption of a network includes at least one terminal to receive a plurality of requests to route data from a plurality of data sources to a plurality of data sinks, where the data sources and the data sinks are connected to each other through a plurality of network nodes forming the network, and a network configuration unit. The network configuration unit includes a selection module configured to select a configuration of the network nodes that allows the network to have a lowest overall power consumption of the network among a plurality of configurations of the network, and an output module configured to output a plurality of instruction signals to the network nodes to perform the network configuration. A network path for transmitting a network flow is selected that does not allow the network flow to be split and flow through another network path.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: March 5, 2013
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Puneet Sharma, Brandon Heller, Priya Mahadevan, Sujata Banerjee, Xiaoyun Zhu, Ram Swaminathan, Parthasarathy Ranganathan
  • Publication number: 20130046904
    Abstract: Example management processors, methods and articles of manufacture are disclosed. A disclosed example management processor includes a network card interface to communicatively couple the management processor to an operating environment, and a request processor to forward a received external management request to the operating environment via the network card interface, and to combine response information received from the operating environment with response information generated at the management processor.
    Type: Application
    Filed: August 18, 2011
    Publication date: February 21, 2013
    Inventors: Jeffrey R. Hilland, Dwight L. Barron, Vanish Talwar, Parthasarathy Ranganathan, Luis E. Luciani, JR.
  • Patent number: 8364829
    Abstract: According to at least one embodiment, a method comprises identifying at least one causal path that includes a node of a distributed computing environment that is of interest. The method further comprises analyzing the identified at least one causal path to determine at least one time interval when the node is active in such causal path, and correlating consumption of a resource by the node to the node's activity in the at least one causal path.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: January 29, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeffrey C. Mogul, Janet L. Wiener, Marcos K. Aguilera, Keith I. Farkas, Parthasarathy Ranganathan
  • Patent number: 8355828
    Abstract: A power model that relates the settings of resource actuators to power consumption levels of the resource actuators and a condition model that relates the settings of the resource actuators to an environmental condition at the location of the at least one entity and a power consumption level of the at least one entity are developed. A constraint optimization problem having an objective function and at least one constraint is formulated, where the objective function computes at least a proportional quantity of a total power consumption level of the resource actuators and the at least one constraint comprises a setpoint environmental condition at a location of the at least entity. A solution to the constraint optimization problem is determined, where the solution provides optimal values for the resource actuator settings.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: January 15, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Niraj Tolia, Zhikui Wang, Manish Marwah, Cullen E. Bash, Parthasarathy Ranganathan, Xiaoyun Zhu
  • Patent number: 8327354
    Abstract: A system for providing virtualization that includes a processor operable to execute one or more machine-readable instructions, the processor having a native instruction set architecture (ISA) and a virtual machine monitor (VMM) operable to host at least a first virtual machine having a first ISA different from the native ISA, the VMM having integrated therein a first dynamic binary translation (DBT) layer to assist in an execution of a first application of the first ISA in the first virtual machine by the processor having the native ISA.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: December 4, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Daniel J. Magenheimer, Parthasarathy Ranganathan, Matthew Chapman
  • Patent number: 8312126
    Abstract: In a system for managing at least one computer node, a first device is configured to perform out-of-band operations in the at least one computing node. The system also includes a second device configured to perform compute-intensive tasks in the at least one computing node and a third device that is external to the at least one computing node configured to perform administration operations for the first device and the second device.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: November 13, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Matteo Monchiero, Parthasarathy Ranganathan, Vanish Talwar
  • Publication number: 20120278651
    Abstract: Embodiments herein relate to a method for remapping data. In an embodiment, it is determined if a first memory block is faulty. A pointer is stored to the first memory block and a pointer flag of the first memory block is set when the first memory block is faulty. Data previously stored at the first memory block is written to a second memory block, where the pointer points to a location of the second memory block.
    Type: Application
    Filed: April 28, 2011
    Publication date: November 1, 2012
    Inventors: Naveen Muralimanohar, Doe Hyun Yoon, Jichuan Chang, Parthasarathy Ranganathan, Norman Paul Jouppi
  • Publication number: 20120278650
    Abstract: Methods, apparatus and articles of manufacture for controlling nanostore operation based on monitored performance are disclosed. An example method disclosed herein comprises monitoring performance of a nanostore, the nanostore including compute logic and a datastore accessible via the compute logic, and controlling operation of the nanostore in response to detecting a performance indicator associated with wearout of the compute logic to permit the compute logic to continue to access the datastore.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 1, 2012
    Inventors: Naveen Muralimanohar, Parthasarathy Ranganathan, Jichuan Chang
  • Publication number: 20120268983
    Abstract: A memory device is provided. The memory device comprises an array of memory cells, each including a volume of material that can stably exhibit at least two different physical states that are each associated with a different data value, word lines that each interconnects a row of memory cells within the array of memory cells to a word-line driver, and bit lines that each interconnects a column of memory cells, through a bit-line driver, to a write driver that is controlled, during a WRITE operation, to write an input data value to an activated memory cell at the intersection of the column of memory cells and an activated row of memory cells by generating a current density within the memory cells that corresponds to retention/endurance characteristics of the memory cell dynamically assigned to the memory cell by a memory controller, operating system, or other control functionality.
    Type: Application
    Filed: April 22, 2011
    Publication date: October 25, 2012
    Inventors: Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan
  • Publication number: 20120272036
    Abstract: An adaptive, memory system is provided. The adaptive memory system has a number of physical-memory devices and a memory controller that creates and maintains a logical address space to which the physical-memory devices and data-storage allocations are mapped, and through which mapping the memory controller matches static, dynamic, and dynamically-adjustable retention and resiliency characteristics of portions of the physical-memory devices with specified retention and resiliency characteristics specified for the data-storage allocations.
    Type: Application
    Filed: April 23, 2011
    Publication date: October 25, 2012
    Inventors: Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Doe Hyun Yoon, Norman Paul Jouppi
  • Publication number: 20120272039
    Abstract: A memory component or subsystem is provided. The memory comprises one or more memory devices and one or more write controllers within each of the one or more memory devices that each controls memory-device components to write input data values into a plurality of memory cells within a memory device that represents a unit of stored data addressed by a logical-address-space address, the write controller applying a current to the plurality of memory cells during a WRITE operation with a magnitude that corresponds to a retention value associated with the logical-address-space address.
    Type: Application
    Filed: April 23, 2011
    Publication date: October 25, 2012
    Inventors: Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan
  • Publication number: 20120254507
    Abstract: A write-absorbing, volatile memory buffer for use with a processor module and a non-volatile memory is disclosed. The write-absorbing buffer operates as a dirty cache that can be used to look up both read and write requests, although allocating new blocks only for write requests and not read requests. The blocks are small sized, and a write-only least-recently used cache replacement policy is used to transfer data in the blocks to the non-volatile memory. The write-absorbing buffer can be used to store copy-on-write pages for at least one virtual machine associated with the processor module and reduce write overhead to the non-volatile memory.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 4, 2012
    Inventors: Jichuan Chang, Parthasarathy Ranganathan, David Roberts
  • Publication number: 20120239799
    Abstract: Systems, methods, and machine-readable and executable instructions are provided for network system management. Network system management can include receiving a network system size and a number of system parameters. Network system management can also include receiving a desired monitoring performance and a desired monitoring quality. Furthermore, network system management can include generating a monitoring system topology for a monitoring and analysis system based on the network system size, the number of system parameters, the desired monitoring performance, and the desired monitoring quality.
    Type: Application
    Filed: March 17, 2011
    Publication date: September 20, 2012
    Inventors: Chengwei Wang, Vanish Talwar, Parthasarathy Ranganathan