Abstract: A memory device and its operation reduce the impact of a parasitic wire Resistance and Capacitance (RC) in the memory device. At least one of a rise transition and a fall transition of a signal transmitted by a long metal line is sensed by a sense circuit of a signal boosting circuit. At least one of a Pull Up (PU) circuit and a Pull Down (PD) circuit of the signal boosting circuit is enabled to speed-up one or both of the rise transition and the fall transition of the signal transmitted by the long metal line. The duration of an operation of one of the PU circuit and the PD circuit may be controlled using a control signal.

Abstract: The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device.

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device.

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device.

Abstract: A bitline precharge system is provided for a semiconductor memory device. The bitline precharge system comprises a voltage comparator circuit to output a reference voltage signal based on an input wordline voltage supply level (VDDWL), and a periphery power supply voltage (VDDP) level. A voltage control circuit is electrically coupled to a periphery power supply and the voltage comparator circuit to output a precharge voltage (VDDM) level based on the reference voltage signal and the periphery power supply voltage (VDDP) level. A bitline precharge circuit is electrically coupled to the voltage control circuit and a plurality of bitlines of the memory device to precharge the plurality of bitlines based on the precharge voltage (VDDM) level in response to a precharge enable signal during one of a read operation to read data from the memory device and a write operation to write data from the memory device.

Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the A output of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

Abstract: An apparatus includes a NMOS transistor having a drain, a first PMOS transistor having a drain connected to the drain of the NMOS transistor, a level shifter having an input and an output, the input of the level shifter being connected to the drain of the NMOS transistor and the drain of the first PMOS transistor, a first digital logic circuit having a drain and a gate, a first inverter having an input connected to the Aoutput of the level shifter and the drain of the first digital logic circuit, and a second digital logic circuit having an output connected to the gate of the first digital logic circuit, at least one condition being set in the apparatus during a read operation.

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

Abstract: The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

Abstract: Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.

Abstract: Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

Abstract: Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.

Abstract: A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.