Abstract: A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis.

Abstract: An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations.

Abstract: A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis.

Abstract: Supply voltage compensated tracking circuit in a split-rail static random access memory (SRAM). The circuit includes a tracking circuit for tracking a delay required for generating sense amplifier enable (SE) signal in a memory. The tracking circuit receives an array supply voltage (VDDAR) and a periphery supply voltage (VDDPR). Further, the circuit includes a discharge control circuit, operatively coupled to the tracking circuit, for increasing delay in activating a first transistor of the tracking circuit when VDDAR is higher than VDDPR; and a contention circuit including an output coupled to the first transistor, for delaying a discharge path activation through the first transistor when VDDAR is lower than the VDDPR.

Abstract: An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations.