Patents by Inventor Pascal Fornara

Pascal Fornara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110153245
    Abstract: An integrated circuit includes non-volatile storage configured to secretly store a digital word, the value of which forms an identification code. The integrated circuit also includes control circuitry configured to receive the digital word and to generate transient electrical currents or transient voltages, the characteristics of which depend on the value of the digital word. There is an electrically conductive network configured to be passed through by the electrical currents or receive the transient voltages so as to generate an electromagnetic field that identifies the integrated circuit.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 23, 2011
    Applicant: STMicroelectronics SA
    Inventors: Pascal FORNARA, Mathieu Lisart
  • Publication number: 20110108902
    Abstract: A non-volatile memory including at least first and second memory cells each including a storage MOS transistor with dual gates and an insulation layer provided between the two gates. The insulation layer of the storage transistor of the second memory cell includes at least one portion that is less insulating than the insulation layer of the storage transistor of the first memory cell.
    Type: Application
    Filed: May 12, 2009
    Publication date: May 12, 2011
    Applicant: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Publication number: 20110080190
    Abstract: A method for protecting, against laser attacks, an integrated circuit chip formed inside and on top of a semiconductor substrate and including in the upper portion of the substrate an active portion in which are formed components, this method including the steps of: forming in the substrate a gettering area extending under the active portion, the upper limit of the area being at a depth ranging between 5 and 50 ?m from the upper surface of the substrate; and introducing diffusing metal impurities into the substrate.
    Type: Application
    Filed: October 4, 2010
    Publication date: April 7, 2011
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Publication number: 20110079881
    Abstract: An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 ?m from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 1017 and 1018 atoms/cm3.
    Type: Application
    Filed: October 4, 2010
    Publication date: April 7, 2011
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Publication number: 20100321049
    Abstract: A element for identifying an integrated circuit chip having identical diffused resistors connected as a Wheatstone bridge.
    Type: Application
    Filed: June 15, 2010
    Publication date: December 23, 2010
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Publication number: 20100315108
    Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.
    Type: Application
    Filed: June 10, 2010
    Publication date: December 16, 2010
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Publication number: 20100308898
    Abstract: An integrated circuit may include a region containing a thermoelectric material and be configured to be subjected to a temperature gradient resulting from a flow of an electric current in a part of the integrated circuit during its operation, and an electrically conducting output coupled to the region for delivering the electrical energy produced by thermoelectric material.
    Type: Application
    Filed: June 3, 2010
    Publication date: December 9, 2010
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Christian RIVERO, Pascal Fornara
  • Publication number: 20100158072
    Abstract: A device for monitoring the temperature surrounding a circuit, including: a charge storage element; a charge evacuation device; and a thermo-mechanical switch connecting the storage element to the evacuation element, the switch being capable of closing without the circuit being electrically powered, when the temperature exceeds a threshold.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 24, 2010
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Publication number: 20100059766
    Abstract: An integrated circuit including a substrate of a semiconductor material and first metal portions of a first metallization level or of a first via level defining pixels of an image. The pixels are distributed in first pixels, for each of which the first metal portion is connected to the substrate, and in second pixels, for each of which the first metal portion is separated from the substrate by at least one insulating portion.
    Type: Application
    Filed: August 10, 2009
    Publication date: March 11, 2010
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Publication number: 20100052128
    Abstract: An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion.
    Type: Application
    Filed: August 7, 2009
    Publication date: March 4, 2010
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Publication number: 20090146214
    Abstract: A method for manufacturing a cell of a non-volatile electrically erasable and programmable memory including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with an insulating layer including a thinned down portion and having a first surface common with the substrate and a second surface opposite to the first surface; and incorporating nitrogen at the level of the second surface, whereby the maximum nitrogen concentration is closer to the second surface than to the first surface.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 11, 2009
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Pascal FORNARA