Patents by Inventor Pascal Fornara

Pascal Fornara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8872177
    Abstract: A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 28, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Pascal Fornara
  • Publication number: 20140266562
    Abstract: An integrated circuit, comprising an electrical-switching mechanical device in a housing having at least one first thermally deformable assembly including a beam held in at least two different locations by at least two arms secured to edges of the housing, the beam and the arms being metallic and situated within the same first metallization level and an electrically conductive body, wherein the said first thermally deformable assembly has at least one first configuration at a first temperature and a second configuration when at least one is at a second temperature different from the first temperature, wherein the beam is at a distance from the body in the first configuration and in contact with the said body and immobilized by the said body in the second configuration and establishing or prohibiting an electrical link passing through the body and through the beam.
    Type: Application
    Filed: May 29, 2014
    Publication date: September 18, 2014
    Inventors: Antonio Di-Giacomo, Christian Rivero, Pascal Fornara
  • Patent number: 8835923
    Abstract: The semiconductor wafer for a silicon-on-insulator integrated circuit comprises an insulating region located between a first semiconductor substrate intended to receive the integrated circuit and a second semiconductor substrate containing at least one buried layer comprising at least one metal silicide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 16, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Patent number: 8830761
    Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Olivier Pizzuto, Stephan Niel, Philippe Boivin, Pascal Fornara, Laurent Lopez, Arnaud Regnier
  • Publication number: 20140209141
    Abstract: Method for generation of electrical power within a three-dimensional integrated structure comprising several elements electrically interconnected by a link device, the method comprising the production of a temperature gradient in at least one region of the link device resulting from the operation of at least one of the said elements, and the production of electrical power using at least one thermo-electric generator comprising at least one assembly of thermocouples electrically connected in series and thermally connected in parallel and contained within the said region subjected to the said temperature gradient.
    Type: Application
    Filed: July 5, 2012
    Publication date: July 31, 2014
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 8779552
    Abstract: An integrated circuit chip formed inside and on top of a semiconductor substrate and including: in the upper portion of the substrate, an active portion in which components are formed; and under the active portion and at a depth ranging between 5 and 50 ?m from the upper surface of the substrate, an area comprising sites for gettering metal impurities and containing metal atoms at a concentration ranging between 1017 and 1018 atoms/cm3.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Patent number: 8759898
    Abstract: A non-volatile memory including at least first and second memory cells each including a storage MOS transistor with dual gates and an insulation layer provided between the two gates. The insulation layer of the storage transistor of the second memory cell includes at least one portion that is less insulating than the insulation layer of the storage transistor of the first memory cell.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: June 24, 2014
    Assignee: STMicroelectronics S.A.
    Inventor: Pascal Fornara
  • Publication number: 20140167908
    Abstract: An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations.
    Type: Application
    Filed: February 20, 2014
    Publication date: June 19, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero, Antonio di-Giacomo
  • Publication number: 20140138814
    Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.
    Type: Application
    Filed: October 9, 2013
    Publication date: May 22, 2014
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Abderrezak Marzaki, Yoann Goasduff, Virginie Bidal, Pascal Fornara
  • Patent number: 8729668
    Abstract: An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Arnaud Regnier
  • Patent number: 8730707
    Abstract: The programming of a read-only memory formed of MOS transistors is set by a mask for forming an insulating layer prior to the forming of contacts of active regions of the transistors. The programming of the read-only memory cannot be determined by visible inspection of the memory.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Pascal Fornara
  • Publication number: 20140133517
    Abstract: A device for monitoring the temperature surrounding a circuit, including: a charge storage element; a charge evacuation device; and a thermo-mechanical switch connecting the storage element to the evacuation element, the switch being capable of closing without the circuit being electrically powered, when the temperature exceeds a threshold.
    Type: Application
    Filed: January 22, 2014
    Publication date: May 15, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christain Rivero
  • Patent number: 8704327
    Abstract: An integrated circuit, comprising a capacitive device having a thermally variable capacitive value and comprising a thermally deformable assembly disposed within an enclosure, and comprising an electrically-conducting fixed body and a beam held at least two different locations by at least two arms rigidly attached to edges of the enclosure, the beam and the arms being metal and disposed within the first metallization level. A part of the said thermally deformable assembly may form a first electrode of the capacitive device and a part of the said fixed body may form a second electrode of the capacitive device. The thermally deformable assembly has a plurality of configurations corresponding respectively to various temperatures of the said assembly and resulting in a plurality of distances separating the two electrodes and various capacitive values in the capacitive device corresponding to the plurality of distances.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: April 22, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Antonio di-Giacomo
  • Patent number: 8692247
    Abstract: An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: April 8, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero, Antonio di-Giacomo
  • Patent number: 8672540
    Abstract: A device for monitoring the temperature surrounding a circuit, including: a charge storage element; a charge evacuation device; and a thermo-mechanical switch connecting the storage element to the evacuation element, the switch being capable of closing without the circuit being electrically powered, when the temperature exceeds a threshold.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: March 18, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Publication number: 20140070829
    Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.
    Type: Application
    Filed: November 18, 2013
    Publication date: March 13, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Publication number: 20140026670
    Abstract: A method for manufacturing an integrated circuit includes forming in a substrate a measuring circuit sensitive to mechanical stresses and configured to supply a measurement signal representative of mechanical stresses exerted on the measuring circuit. The measuring circuit is positioned such that the measurement signal is also representative of mechanical stresses exerted on a functional circuit of the integrated circuit. A method of using the integrated circuit includes determining from the measurement signal the value of a parameter of the functional circuit predicted to mitigate an impact of the variation in mechanical stresses on the operation of the functional circuit, and supplying the functional circuit with the determined value of the parameter.
    Type: Application
    Filed: July 29, 2013
    Publication date: January 30, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Publication number: 20140027881
    Abstract: An electric charge flow element including, on an insulating support, a stack of a first electrode, of a dielectric layer having at least one portion capable of letting charges flow by tunnel effect, and of a second electrode, wherein at least one of the electrodes is made of undoped polysilicon.
    Type: Application
    Filed: July 29, 2013
    Publication date: January 30, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Pascal Fornara
  • Patent number: 8618821
    Abstract: A device for detecting the thinning down of the substrate of an integrated circuit chip, including, in the active area of the substrate, bar-shaped diffused resistors connected as a Wheatstone bridge, wherein: first opposite resistors of the bridge are oriented along a first direction; the second opposite resistors of the bridge are oriented along a second direction; and the first and second directions are such that a thinning down of the substrate causes a variation of the imbalance value of the bridge.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: December 31, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 8610256
    Abstract: An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: December 17, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero