Patents by Inventor Pascal Fornara

Pascal Fornara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated thermoelectric generator
    Patent number: 9490415
    Abstract: An integrated thermoelectric generator includes a semiconductor. A set of thermocouples are electrically connected in series and thermally connected in parallel. The set of thermocouples include parallel semiconductor regions. Each semiconductor region has one type of conductivity from among two opposite types of conductivity. The semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: November 8, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Metallic Device Having Mobile Element in a Cavity of the BEOL of an Integrated Circuit
    Publication number: 20160293540
    Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.
    Type: Application
    Filed: October 22, 2015
    Publication date: October 6, 2016
    Inventors: Christian Rivero, Pascal Fornara, Sebastian Orellana
  • Device for monitoring the temperature of an element
    Patent number: 9459157
    Abstract: A device for monitoring the temperature surrounding a circuit, including: a charge storage element; a charge evacuation device; and a thermo-mechanical switch connecting the storage element to the evacuation element, the switch being capable of closing without the circuit being electrically powered, when the temperature exceeds a threshold.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: October 4, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • ZENER DIODE HAVING AN ADJUSTABLE LOW BREAKDOWN VOLTAGE
    Publication number: 20160276496
    Abstract: The present disclosure relates to a Zener diode including a cathode region having a first conductivity type, formed on a surface of a semiconductor substrate having a second conductivity type. The Zener diode includes an anode region having the second conductivity type, formed beneath the cathode region. One or more trench isolations isolate the cathode and anode regions from a remainder of the substrate. A first conducting region is configured to, when subjected to an adequate voltage, generate a first electric field perpendicular to an interface between the cathode and anode regions. A second conducting region is configured to, when subjected to an adequate voltage, generate a second electric field parallel to the interface between the cathode and anode regions.
    Type: Application
    Filed: December 9, 2015
    Publication date: September 22, 2016
    Inventors: Roberto Simola, Pascal Fornara
  • ZENER DIODE HAVING AN ADJUSTABLE BREAKDOWN VOLTAGE
    Publication number: 20160276447
    Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.
    Type: Application
    Filed: December 9, 2015
    Publication date: September 22, 2016
    Inventors: Roberto Simola, Pascal Fornara
  • Method of Operating an Integrated Switchable Capacitive Device
    Publication number: 20160203917
    Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.
    Type: Application
    Filed: March 22, 2016
    Publication date: July 14, 2016
    Inventors: Pascal Fornara, Christian Rivero
  • Electrically controllable integrated switch
    Patent number: 9355802
    Abstract: An integrated circuit includes an interconnection part with several metallization levels. An electrically activatable switching device within the interconnection part has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 31, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Christian Rivero, Pascal Fornara, Antonio di-Giacomo, Brice Arrazat
  • Method for detecting electrical energy produced from a thermoelectric material contained in an integrated circuit
    Patent number: 9331027
    Abstract: An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: May 3, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Method for Producing an Integrated Circuit Pointed Element, and Corresponding Integrated Circuit
    Publication number: 20160116631
    Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Inventors: Abderrezak Marzaki, Yoann Goasduff, Virginie Bidal, Pascal Fornara
  • Method of making an integrated switchable capacitive device
    Patent number: 9324706
    Abstract: A method is provided for forming an integrated circuit chip with a variable capacitor disposed in a metallization. A back end of line metallization is formed over the semiconductor substrate. The variable capacitor is formed within a cavity of the back end of line metallization. The variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer of the back end of line metallization, a second main capacitor electrode electrically connected to a second metal layer of the back end of line metallization and vertically spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: April 26, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Method of Wireless Communication using Thermoelectric Generators
    Publication number: 20160111470
    Abstract: Method of Wireless Communication using Thermoelectric Generators Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.
    Type: Application
    Filed: December 22, 2015
    Publication date: April 21, 2016
    Inventors: Pascal Fornara, Christian Rivero
  • Electrically Controllable Integrated Switch
    Publication number: 20160107886
    Abstract: Methods of forming and operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 21, 2016
    Inventors: Christian Rivero, Pascal Fornara, Antonio di-Giacomo, Brice Arrazat
  • INTEGRATED CIRCUIT COMPRISING COMPONENTS, FOR EXAMPLE NMOS TRANSISTORS, HAVING ACTIVE REGIONS WITH RELAXED COMPRESSIVE STRESSES
    Publication number: 20160093696
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 31, 2016
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Method of Making an Integrated Switchable Capacitive Device
    Publication number: 20160093609
    Abstract: A method is provided for forming an integrated circuit chip with a variable capacitor disposed in a metallization. A back end of line metallization is formed over the semiconductor substrate. The variable capacitor is formed within a cavity of the back end of line metallization. The variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer of the back end of line metallization, a second main capacitor electrode electrically connected to a second metal layer of the back end of line metallization and vertically spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode.
    Type: Application
    Filed: December 2, 2015
    Publication date: March 31, 2016
    Inventors: Pascal Fornara, Christian Rivero
  • METHOD FOR FABRICATION OF AN INTEGRATED CIRCUIT RENDERING A REVERSE ENGINEERING OF THE INTEGRATED CIRCUIT MORE DIFFICULT AND CORRESPONDING INTEGRATED CIRCUIT
    Publication number: 20160064339
    Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.
    Type: Application
    Filed: August 18, 2015
    Publication date: March 3, 2016
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero, Guilhem Bouton
  • Integrated Thermoelectric Generator
    Publication number: 20160056364
    Abstract: An integrated thermoelectric generator includes a semiconductor. A set of thermocouples are electrically connected in series and thermally connected in parallel. The set of thermocouples include parallel semiconductor regions. Each semiconductor region has one type of conductivity from among two opposite types of conductivity. The semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity.
    Type: Application
    Filed: November 2, 2015
    Publication date: February 25, 2016
    Inventors: Pascal Fornara, Christian Rivero
  • Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses
    Patent number: 9269771
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: February 23, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Guilhem Bouton, Pascal Fornara
  • Component, for example NMOS transistor, with active region with relaxed compression stresses, and fabrication method
    Patent number: 9263518
    Abstract: An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by an insulating region. The insulating region is formed to includes at least one area in which the insulating region has two insulating extents that are mutually separated from each other by a separation region formed by a part of the substrate.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: February 16, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Guilhem Bouton, Pascal Fornara
  • EEPROM CELL WITH CHARGE LOSS
    Publication number: 20160033937
    Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.
    Type: Application
    Filed: October 14, 2015
    Publication date: February 4, 2016
    Inventor: Pascal Fornara
  • Integrated switchable capacitive device
    Patent number: 9230907
    Abstract: An integrated circuit includes a substrate. A fixed main capacitor electrode is disposed in a metal layer overlying the substrate. A second main capacitor electrode is disposed in a metal layer and spaced from the fixed main capacitor electrode. A movable capacitor electrode is disposed adjacent the fixed main capacitor electrode. The movable capacitor electrode is switchable between a first configuration in which the movable capacitor electrode and fixed main capacitor electrode are mutually spaced out in such a manner as to form an auxiliary capacitor electrically connected to the main capacitor. In a second configuration, the movable capacitor electrode and the fixed main capacitor electrode are in electrical contact in such a manner as to give a second capacitive value.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: January 5, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Christian Rivero