Patents by Inventor Patrick A. Van Cleemput
Patrick A. Van Cleemput has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12148623Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.Type: GrantFiled: November 18, 2019Date of Patent: November 19, 2024Assignee: Lam Research CorporationInventors: Patrick A. van Cleemput, Shruti Vivek Thombare, Michal Danek
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Patent number: 12112980Abstract: Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO2 and SiN can be selectively etched using a plasma formed in an H2-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% H2. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.Type: GrantFiled: June 24, 2021Date of Patent: October 8, 2024Assignee: Lam Research CorporationInventors: Patrick A. van Cleemput, Seshasayee Varadarajan, Bart J. van Schravendijk
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Publication number: 20240297075Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.Type: ApplicationFiled: May 13, 2024Publication date: September 5, 2024Inventors: Shruti Vivek THOMBARE, Raashina HUMAYUN, Michal DANEK, Chiukin Steven LAI, Joshua COLLINS, Hanna BAMNOLKER, Griffin John KENNEDY, Gorun BUTAIL, Patrick A. VAN CLEEMPUT
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Patent number: 12074029Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.Type: GrantFiled: July 21, 2022Date of Patent: August 27, 2024Assignee: Lam Research CorporationInventors: Patrick A. Van Cleemput, Shruti Vivek Thombare, Michal Danek
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Publication number: 20240271281Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: ApplicationFiled: April 3, 2024Publication date: August 15, 2024Inventors: Joshua COLLINS, Griffin John KENNEDY, Hanna BAMNOLKER, Patrick A. VAN CLEEMPUT, Seshasayee VARADARAJAN
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Patent number: 12051589Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, formation of spacers involves deposition of a tin oxide layer on a semiconductor substrate having multiple protruding features. The deposition is performed in a deposition apparatus having a controller with program instructions configured to cause sequential contacting of the semiconductor substrate with a tin-containing precursor and an oxygen-containing precursor such as to coat the semiconductor substrate having the protruding features with a tin oxide layer. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the semiconductor substrate.Type: GrantFiled: September 21, 2021Date of Patent: July 30, 2024Assignee: Lam Research CorporationInventors: David Charles Smith, Richard Wise, Arpan Pravin Mahorowala, Patrick A van Cleemput, Bart J. van Schravendijk
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Publication number: 20240234152Abstract: Provided herein are low resistance metallization stack structures for 3D-NAND applications and related methods of fabrication. In some embodiments, thin metal oxynitride nucleation layers are deposited on dielectric material followed by deposition of a pure metal conductor using process conditions that increase non-molybdenum component element content at the oxynitride-dielectric interface. Certain embodiments of the methods described below convert less than all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: ApplicationFiled: February 18, 2022Publication date: July 11, 2024Inventors: Lawrence Schloss, Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Sang-Hyeob Lee, Patrick van Cleemput, Sanjay Gopinath
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Publication number: 20240172413Abstract: A method for reducing bending of word lines in a memory cell includes a) providing a substrate including a plurality of word lines arranged adjacent to one another and above a plurality of transistors; b) depositing a layer of film on the plurality of word lines using a deposition process; c) after depositing the layer of film, measuring word line bending; d) comparing the word line bending to a predetermined range; e) based on the word line bending, adjusting at least one of nucleation delay and grain size of the deposition process; and f) repeating b) to e) one or more times using one or more substrates, respectively, until the word line bending is within the predetermined range.Type: ApplicationFiled: December 22, 2023Publication date: May 23, 2024Inventors: Gorun BUTAIL, Shruti THOMBARE, Ishtak KARIM, Patrick VAN CLEEMPUT
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Patent number: 11970776Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: GrantFiled: January 27, 2020Date of Patent: April 30, 2024Assignee: Lam Research CorporationInventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Patrick A. van Cleemput, Seshasayee Varadarajan
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Publication number: 20240136192Abstract: Provided herein are low resistance metallization stack structures for 3D-NAND applications and related methods of fabrication. In some embodiments, thin metal oxynitride nucleation layers are deposited on dielectric material followed by deposition of a pure metal conductor using process conditions that increase non-molybdenum component element content at the oxynitride-dielectric interface. Certain embodiments of the methods described below convert less than all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.Type: ApplicationFiled: February 18, 2022Publication date: April 25, 2024Inventors: Lawrence Schloss, Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Sang-Hyeob Lee, Patrick van Cleemput, Sanjay Gopinath
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Publication number: 20240084443Abstract: A showerhead includes a plurality of plenums and a plurality of through holes positioned in the plurality of plenums. The plenums are stacked in a sequential order in an axial direction perpendicular to a semiconductor substrate. The plenums extend radially fully across the semiconductor substrate. The plenums are disjoint from each other and are configured to respectively supply a first metal precursor, a second metal precursor, and a reactant via the respective plenums without intermixing the first metal precursor, the second metal precursor, and the reactant in the plenums. The through holes of the respective plenums are arranged in a radial direction, which is perpendicular to the axial direction, in the same sequential order as the sequential order of the plenums. The through holes of the plenums open along a flat surface at a bottom of the showerhead. The flat surface extends radially fully across the bottom of the showerhead.Type: ApplicationFiled: November 27, 2023Publication date: March 14, 2024Inventors: Ilanit FISHER, Raashina Humayun, Michal Danek, Patrick Van Cleemput, Shruti Thombare
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Patent number: 11887846Abstract: An Atomic Layer Deposition (ALD) method to deposit a metal oxide layer onto an organic photoresist on a substrate using a highly reactive organic metal precursor. The deposition method protects the organic photoresist from loss and degradation from exposure to oxygen species during subsequent ALD cycles. The organic metal precursor may be an amino type precursor or a methoxy type precursor.Type: GrantFiled: February 28, 2020Date of Patent: January 30, 2024Assignee: Lam Research CorporationInventors: Akhil Singhal, Patrick Van Cleemput
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Publication number: 20240030031Abstract: Thin tin oxide films can be used in semiconductor device manufacturing. In one implementation, a method of processing a semiconductor substrate includes: providing a semiconductor substrate having a plurality of protruding features residing on an etch stop layer material, and an exposed tin oxide layer in contact with both the protruding features and the etch stop layer material, where the tin oxide layer covers both sidewalls and horizontal surfaces of the protruding features; and then completely removing the tin oxide layer from horizontal surfaces of the semiconductor substrate without completely removing the tin oxide layer residing at the sidewalls of the protruding features. Next, the protruding features can be removed without completely removing the tin oxide layer that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers.Type: ApplicationFiled: October 6, 2023Publication date: January 25, 2024Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick A. Van Cleemput, Bart J. Van Schravendijk
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Patent number: 11864372Abstract: A method for reducing bending of word lines in a memory cell includes a) providing a substrate including a plurality of word lines arranged adjacent to one another and above a plurality of transistors; b) depositing a layer of film on the plurality of word lines using a deposition process; c) after depositing the layer of film, measuring word line bending; d) comparing the word line bending to a predetermined range; e) based on the word line bending, adjusting at least one of nucleation delay and grain size of the deposition process; and f) repeating b) to e) one or more times using one or more substrates, respectively, until the word line bending is within the predetermined range.Type: GrantFiled: November 25, 2019Date of Patent: January 2, 2024Assignee: Lam Research CorporationInventors: Gorun Butail, Shruti Thombare, Ishtak Karim, Patrick Van Cleemput
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Patent number: 11827976Abstract: A method includes arranging a substrate in a processing chamber, and exposing the substrate to a gas mixture including a first metal precursor gas and a second metal precursor gas to deposit a first metal precursor and a second metal precursor onto the substrate at the same time. The method further includes purging the processing chamber, supplying a reactant common to both the first metal precursor and the second metal precursor to form a layer of an alloy on the substrate, and purging the processing chamber.Type: GrantFiled: December 6, 2018Date of Patent: November 28, 2023Assignee: LAM RESEARCH CORPORATIONInventors: Ilanit Fisher, Raashina Humayun, Michal Danek, Patrick Van Cleemput, Shruti Thombare
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Patent number: 11784047Abstract: Thin tin oxide films can be used in semiconductor device manufacturing. In one implementation, a method of processing a semiconductor substrate includes: providing a semiconductor substrate having a plurality of protruding features residing on an etch stop layer material, and an exposed tin oxide layer in contact with both the protruding features and the etch stop layer material, where the tin oxide layer covers both sidewalls and horizontal surfaces of the protruding features; and then completely removing the tin oxide layer from horizontal surfaces of the semiconductor substrate without completely removing the tin oxide layer residing at the sidewalls of the protruding features. Next, the protruding features can be removed without completely removing the tin oxide layer that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers.Type: GrantFiled: April 22, 2021Date of Patent: October 10, 2023Assignee: Lam Research CorporationInventors: David Charles Smith, Richard Wise, Arpan Pravin Mahorowala, Patrick A. van Cleemput, Bart J. van Schravendijk
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Publication number: 20230290680Abstract: Provided herein are methods and apparatuses for forming metal films such as tungsten (W) and molybdenum (Mo) films on semiconductor substrates. The methods involve forming a reducing agent layer, then exposing the reducing agent layer to a metal precursor to convert the reducing agent layer to a layer of the metal. In some embodiments, the reducing agent layer is a silicon- (Si-) and boron- (B-) containing layer. The methods may involve forming the reducing agent layer at a first substrate temperature, raising the substrate temperature to a second substrate temperature, and then exposing the reducing agent layer to 10 the metal precursor at the second substrate temperature. The methods may be used to form fluorine-free tungsten or molybdenum films in certain embodiments. Apparatuses to perform the methods are also provided.Type: ApplicationFiled: May 1, 2023Publication date: September 14, 2023Inventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Michal Danek, Shruti Vivek Thombare, Patrick A. van Cleemput, Gorun Butail
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Publication number: 20230260834Abstract: Various embodiments herein relate to methods, apparatus, and systems for forming an interconnect structure, or a portion thereof, on a substrate. In one example, the method includes receiving the substrate in a processing chamber, the substrate having dielectric material exposed within recessed features formed therein; exposing the substrate to plasma to thereby modify a top surface of the dielectric material; forming a metal oxide barrier layer on the modified top surface of the dielectric material, wherein the metal oxide barrier layer is formed through atomic layer deposition and/or chemical vapor deposition. In certain implementations, one or more additional step may be taken to improve processing results, for example to promote nucleation and/or adhesion of relevant layers.Type: ApplicationFiled: June 25, 2021Publication date: August 17, 2023Inventors: Lee J. BROGAN, Patrick A. VAN CLEEMPUT, Matthew Martin HUIE, Kyle Jordan BLAKENEY, Yi Hua LIU
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Patent number: 11670516Abstract: Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.Type: GrantFiled: August 19, 2019Date of Patent: June 6, 2023Assignee: Lam Research CorporationInventors: Karthik S. Colinjivadi, Samantha SiamHwa Tan, Shih-Ked Lee, George Matamis, Yongsik Yu, Yang Pan, Patrick Van Cleemput, Akhil Singhal, Juwen Gao, Raashina Humayun
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Patent number: 11637037Abstract: Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO2 and SiN can be selectively etched using a plasma formed in an Hz-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% Hz. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.Type: GrantFiled: March 20, 2020Date of Patent: April 25, 2023Assignee: Lam Research CorporationInventors: Patrick van Cleemput, Seshasayee Varadarajan, Bart J. van Schravendijk