Patents by Inventor Patrick A. Van Cleemput

Patrick A. Van Cleemput has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220389579
    Abstract: Provided herein are methods and apparatus for deposition of pure metal films. The methods involve the use of oxygen-containing precursors. The metals include molybdenum (Mo) and tungsten (W). To deposit pure films with no more than one atomic percentage oxygen, the reducing agent to metal precursor ratio is significantly greater than 1. Molar ratios of 100:1 to 10000:1 may be used in some embodiments.
    Type: Application
    Filed: July 21, 2022
    Publication date: December 8, 2022
    Inventors: Shruti Vivek THOMBARE, Gorun BUTAIL, Patrick A. VAN CLEEMPUT, Ilanit FISHER
  • Publication number: 20220375792
    Abstract: Embodiments of methods of filling features with molybdenum (Mo) include depositing a first layer of Mo in a feature including an opening and an interior and non-conformally treating the first layer such that regions near the opening preferentially treated over regions in the interior. In some embodiments, a second Mo layer is deposited on the treated first layer. Embodiments of methods of filling features with Mo include controlling Mo precursor flux to transition between conformal and non-conformal fill.
    Type: Application
    Filed: October 14, 2020
    Publication date: November 24, 2022
    Inventors: Lawrence SCHLOSS, Shruti Vivek THOMBARE, Zhongbo YAN, Patrick A. VAN CLEEMPUT, Joshua COLLINS
  • Publication number: 20220356579
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Joshua COLLINS, Griffin John KENNEDY, Hanna BAMNOLKER, Patrick A. VAN CLEEMPUT, Seshasayee VARADARAJAN
  • Publication number: 20220359211
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Patrick A. VAN CLEEMPUT, Shruti Vivek THOMBARE, Michal DANEK
  • Publication number: 20220328317
    Abstract: Provided are methods of filling patterned features with molybdenum (Mo). The methods involve selective deposition of Mo films on bottom metal-containing surfaces of a feature including dielectric sidewalls. The selective growth of Mo on the bottom surface allows bottom-up growth and high quality, void-free fill. Also provided are related apparatus.
    Type: Application
    Filed: September 1, 2020
    Publication date: October 13, 2022
    Applicant: Lam Research Corporation
    Inventors: Jeong-Seok NA, Yao-Tsung HSIEH, Chiukin Steven LAI, Patrick A. VAN CLEEMPUT
  • Publication number: 20220290300
    Abstract: Various showerheads and methods are provided. A showerhead may include a faceplate partially defined by a front surface and a back surface, a back plate having a gas inlet, a first conical frustum surface, and a second conical frustum surface, a plenum volume fluidically connected to the gas inlet and at least partially defined by the gas inlet, the back surface of the faceplate, the first conical frustum surface, and the second conical frustum surface, and a baffle plate positioned within the plenum volume, and having a plurality of baffle plate through-holes extending through the baffle plate. The second conical frustum surface may be positioned radially outwards from the first conical frustum surface with respect to a center axis of the showerhead, and the second conical frustum surface may be positioned along the center axis farther from the gas inlet than the first conical frustum surface.
    Type: Application
    Filed: August 19, 2020
    Publication date: September 15, 2022
    Inventors: Ravi Vellanki, Eric H. Lenz, Vinayakaraddy Gulabal, Sanjay Gopinath, Michal Danek, Prodyut Majumder, Novy Tjokro, Yen-Chang Chen, Shruti Vivek Thombare, Gorun Butail, Patrick A. van Cleemput
  • Publication number: 20220223471
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some implementations, the methods involve providing a tungsten (W)-containing layer on a substrate; and depositing a molybdenum (Mo)-containing layer on the W-containing layer. In some implementations, the methods involve depositing a Mo-containing layer directly on a dielectric or titanium nitride (TiN) substrate without an intervening W-containing layer.
    Type: Application
    Filed: January 31, 2022
    Publication date: July 14, 2022
    Inventors: Shruti Vivek THOMBARE, Raashina HUMAYUN, Michal DANEK, Chiukin Steven LAI, Joshua COLLINS, Hanna BAMNOLKER, Griffin John KENNEDY, Gorun BUTAIL, Patrick A. van Cleemput
  • Publication number: 20220195598
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.
    Type: Application
    Filed: January 27, 2020
    Publication date: June 23, 2022
    Inventors: Joshua Collins, Griffin John Kennedy, Hanna Bamnolker, Patrick A. van Cleemput, Seshasayee Varadarajan
  • Patent number: 11270896
    Abstract: Provided are methods and apparatus for ultraviolet (UV) assisted capillary condensation to form dielectric materials. In some embodiments, a UV driven reaction facilitates photo-polymerization of a liquid phase flowable material. Applications include high quality gap fill in high aspect ratio structures and pore sealing of a porous solid dielectric film. According to various embodiments, single station and multi-station chambers configured for capillary condensation and UV exposure are provided.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: March 8, 2022
    Assignee: Lam Research Corporation
    Inventors: Jonathan D. Mohn, Nicholas Muga Ndiege, Patrick A. van Cleemput, David Fang Wei Chen, Wenbo Liang, Shawn M. Hamilton
  • Publication number: 20220028864
    Abstract: A method for reducing bending of word lines in a memory cell includes a) providing a substrate including a plurality of word lines arranged adjacent to one another and above a plurality of transistors; b) depositing a layer of film on the plurality of word lines using a deposition process; c) after depositing the layer of film, measuring word line bending; d) comparing the word line bending to a predetermined range; e) based on the word line bending, adjusting at least one of nucleation delay and grain size of the deposition process; and f) repeating b) to e) one or more times using one or more substrates, respectively, until the word line bending is within the predetermined range.
    Type: Application
    Filed: November 25, 2019
    Publication date: January 27, 2022
    Inventors: Gorun BUTAIL, Shruti THOMBARE, Ishtak KARIM, Patrick VAN CLEEMPUT
  • Publication number: 20220013365
    Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication, The methods involve forming bulk conductive films on thin low resistivity transition metal layers that have large grain size. The bulk conductive films follow the grains of the low resistivity transition metal films, resulting in large grain size. Also provided are devices including template layers and bulk films.
    Type: Application
    Filed: November 18, 2019
    Publication date: January 13, 2022
    Applicant: Lam Research Corporation
    Inventors: Patrick A. van Cleemput, Shruti Vivek Thombare, Michal Danek
  • Publication number: 20220005694
    Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, formation of spacers involves deposition of a tin oxide layer on a semiconductor substrate having multiple protruding features. The deposition is performed in a deposition apparatus having a controller with program instructions configured to cause sequential contacting of the semiconductor substrate with a tin-containing precursor and an oxygen-containing precursor such as to coat the semiconductor substrate having the protruding features with a tin oxide layer. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the semiconductor substrate.
    Type: Application
    Filed: September 21, 2021
    Publication date: January 6, 2022
    Inventors: David Charles Smith, Richard Wise, Arpan Pravin Mahorowala, Patrick A. van Cleemput, Bart J. van Schravendijk
  • Patent number: 11183383
    Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: November 23, 2021
    Assignee: Lam Research Corporation
    Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick van Cleemput, Bart J. van Schravendijk
  • Publication number: 20210343579
    Abstract: Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO2 and SiN can be selectively etched using a plasma formed in an H2-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% H2. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.
    Type: Application
    Filed: June 24, 2021
    Publication date: November 4, 2021
    Inventors: Patrick A. van Cleemput, Seshasayee Varadarajan, Bart J. van Schravendijk
  • Patent number: 11088019
    Abstract: Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO2 and SiN can be selectively etched using a plasma formed in an H2-containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO2, SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% H2. Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: August 10, 2021
    Assignee: Lam Research Corporation
    Inventors: Patrick A. Van Cleemput, Seshasayee Varadarajan, Bart J. van Schravendijk
  • Publication number: 20210242032
    Abstract: Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.
    Type: Application
    Filed: August 19, 2019
    Publication date: August 5, 2021
    Inventors: Karthik S. COLINJIVADI, Samantha SiamHwa TAN, Shih-Ked LEE, George MATAMIS, Yongsik YU, Yang PAN, Patrick VAN CLEEMPUT, Akhil SINGHAL, Juwen GAO, Raashina HUMAYUN
  • Publication number: 20210242019
    Abstract: Thin tin oxide films can be used in semiconductor device manufacturing. In one implementation, a method of processing a semiconductor substrate includes: providing a semiconductor substrate having a plurality of protruding features residing on an etch stop layer material, and an exposed tin oxide layer in contact with both the protruding features and the etch stop layer material, where the tin oxide layer covers both sidewalls and horizontal surfaces of the protruding features; and then completely removing the tin oxide layer from horizontal surfaces of the semiconductor substrate without completely removing the tin oxide layer residing at the sidewalls of the protruding features. Next, the protruding features can be removed without completely removing the tin oxide layer that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers.
    Type: Application
    Filed: April 22, 2021
    Publication date: August 5, 2021
    Inventors: David Charles Smith, Richard Wise, Arpan Pravin Mahorowala, Patrick A. van Cleemput, Bart J. van Schravendijk
  • Patent number: 11031245
    Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: June 8, 2021
    Assignee: Lan Research Corporation
    Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick A. Van Cleemput, Bart J. van Schravendijk
  • Publication number: 20210140043
    Abstract: Provided herein are methods and apparatus for deposition of pure metal films. The methods involve the use of oxygen-containing precursors. The metals include molybdenum (Mo) and tungsten (W). To deposit pure films with no more than one atomic percentage oxygen, the reducing agent to metal precursor ratio is significantly greater than 1. Molar ratios of 100:1 to 10000:1 may be used in some embodiments.
    Type: Application
    Filed: July 25, 2019
    Publication date: May 13, 2021
    Inventors: Shruti Vivek Thombare, Gorun Butail, Patrick A. van Cleemput, Ilanit Fisher
  • Patent number: 10957514
    Abstract: Provided are apparatuses and methods for performing deposition and etch processes in an integrated tool. An apparatus may include a plasma processing chamber that is a capacitively-coupled plasma reactor, and the plasma processing chamber can include a showerhead that includes a top electrode and a pedestal that includes a bottom electrode. The apparatus may be configured with an RF hardware configuration so that an RF generator may power the top electrode in a deposition mode and power the bottom electrode in an etch mode. In some implementations, the apparatus can include one or more switches so that at least an HFRF generator is electrically connected to the showerhead in a deposition mode, and the HFRF generator and an LFRF generator is electrically connected to the pedestal and the showerhead is grounded in the etch mode.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 23, 2021
    Assignee: Lam Research Corporation
    Inventors: Akhil Singhal, Patrick A. van Cleemput, Martin E. Freeborn, Bart J. van Schravendijk