Patents by Inventor Patrick A. Van Cleemput

Patrick A. Van Cleemput has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6867152
    Abstract: A rapid vapor deposition (RVD) method conformally deposits a dielectric material on small features of a substrate surface. The resulting dielectric film has a low dielectric constant, low wet etch rate, low film shrinkage and low stress hysteresis, appropriate for various integrated circuit dielectric gap fill applications such as shallow trench isolation. The method includes the following two principal operations: depositing a thin conformal and saturated layer of aluminum-containing precursor over some or all of the substrate surface; and exposing the saturated layer of aluminum-containing precursor to a silicon-containing precursor gas to form a dielectric layer. In some cases, the substrate temperatures during contact with silicon-containing precursor are greater than about 250 degree Celsius to produce an improved film. In other cases, post-deposition anneal process may be used to improve properties of the film.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: March 15, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Dennis M. Hausmann, Adrianne K. Tipton, Patrick A. Van Cleemput, Bunsen Nie, Francisco J. Juarez, Teresa Pong
  • Patent number: 6846391
    Abstract: A process for filling high aspect ratio gaps on substrates uses conventional high density plasma deposition processes to deposit fluorine-doped films, with an efficient sputtering inert gas, such as Ar, replaced or reduced with an inefficient sputtering inert gas such as He and/or hydrogen. By reducing the sputtering component, sidewall deposition from the sputtered material is reduced. Consequently, gaps with aspect ratios greater than 3.0:1 and spacings between lines less than 0.13 microns can be filled with low dielectric constant films without the formation of voids and without damaging circuit elements.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: January 25, 2005
    Assignee: Novellus Systems
    Inventors: George D. Papasouliotis, Robert D. Tas, Patrick A. Van Cleemput, Bart van Schravendijk
  • Patent number: 6766810
    Abstract: The present invention pertains to methods and apparatus for controlling the pressure in a supercritical processing system. Active methods for controlling the pressure include anticipating a pressure deviation due to a solute addition to a system, and changing the pressure within the system to compensate for the deviation. In this way, a desired pressure is achieved when the solute is added, without phase separation of the solute from the solvent. Pressure is adjusted by changing the volume of the supercritical processing system. Passive methods include adjusting the pressure of a supercritical system by changing the volume in response to a pressure deviation from a desired pressure. Apparatus for controlling the pressure in a supercritical processing system are described.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: July 27, 2004
    Assignee: Novellus Systems, Inc.
    Inventor: Patrick A. Van Cleemput
  • Publication number: 20040118812
    Abstract: Methods are described for removing a material from a substrate by dissolving an etchant into a solvent to form a solution; and exposing the substrate to the solution so that the etchant in the solution removes material from the substrate; wherein during the exposure the solution is maintained in a supercritical or near-supercritical phase. The described methods can include additional steps, such as exposing a precursor of the material to a reagent to form the material, and depositing a second material onto the substrate after removing the material from the substrate.
    Type: Application
    Filed: August 7, 2003
    Publication date: June 24, 2004
    Inventors: James J. Watkins, Patrick A. Van Cleemput, Ronald Powell
  • Publication number: 20040096586
    Abstract: An automated deposition system includes a template deposition chamber that is used to deposit a mesostructured template on a wafer or other substrate, such as an optical lens. A supercritical infusion chamber infuses the mesoporous template with a matrix-forming material that is cured to produce a mesoporous matrix. The template may be removed by thermal, chemical or plasma processing to leave the mesoporous matrix intact.
    Type: Application
    Filed: November 15, 2002
    Publication date: May 20, 2004
    Inventors: Michelle T. Schulberg, Raashina Humayun, Patrick A. Van Cleemput, Wilbert G.M. Van den Hoek
  • Patent number: 6576345
    Abstract: Thin films possessing low dielectric constants (e.g., dielectric constants below 3.0) are formed on integrated circuits or other substrates. Caged-siloxane precursors are linked in such a way as to form dielectric layers, which exhibit low dielectric constants by virtue of their silicon dioxide-like molecular structure and porous nature. Supercritical fluids may be used as the reaction medium and developer both to the dissolve and deliver the caged-siloxane precursors and to remove reagents and byproducts from the reaction chamber and resultant porous film created.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: June 10, 2003
    Inventors: Patrick A. Van Cleemput, Ravi Kumar Laxman, Jen Shu, Michelle T. Schulberg, Bunsen Nie
  • Patent number: 6550484
    Abstract: The present invention pertains to apparatus and methods for maintaining wafer back side, bevel, and front side edge exclusion during supercritical fluid processing. Apparatus of the invention include a pedestal and an exclusion ring. When the exclusion ring is engaged with the pedestal a channel is formed. A reactant-free supercritical fluid is passed through the channel and over a circumferential front edge of a wafer. The flow of reactant-free supercritical fluid protects the bevel and circumferential front edge of the wafer from exposure to reactants in a supercritical processing medium. The back side of the wafer is protected by contact with the pedestal and the flow of reactant-free supercritical fluid. Exclusion rings of the invention, when engaged with their corresponding pedestals make no or very little physical contact with the wafer front side.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: April 22, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Sanjay Gopinath, Patrick A. Van Cleemput, Francisco Juarez, Krishnan Shrinivasan
  • Patent number: 6395150
    Abstract: A process for filling high aspect ratio gaps on substrates uses conventional high density plasma deposition processes, with an efficient sputtering inert gas, such as Ar, replaced or reduced with an He inefficient sputtering inert gas such as He. By reducing the sputtering component, sidewall deposition from the sputtered material is reduced. Consequently, gaps with aspect ratios of 6.0:1 and higher can be filled without the formation of voids and without damaging circuit elements.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: May 28, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: Patrick A. Van Cleemput, George D. Papasouliotis, Mark A. Logan, Bart van Schravendijk, William J. King
  • Publication number: 20020052119
    Abstract: A process for filling high aspect ratio gaps on substrates uses high density plasma deposition processes for depositing a BPSG layer. Deposition at conventional temperatures fills more of high aspect ratio gaps than prior methods. The BPSG layer is then reflowed to fill in any small voids remaining in the high aspect ratio gaps. In another embodiment, the deposition temperature is increased to allow the BPSG layer to reflow in-situ, thereby providing similar void-free high aspect ratio gap fill capabilities.
    Type: Application
    Filed: March 31, 1999
    Publication date: May 2, 2002
    Inventor: PATRICK A. VAN CLEEMPUT
  • Patent number: 6340628
    Abstract: A chemical vapor deposition (CVD) process uses a precursor gas, such as with a siloxane or alkylsilane, and a carbon-dioxide-containing gas, such as CO2 with O2 or CO2 with CxH(2x+1)OH where 1≦x≦5, to deposit a dielectric layer with no photoresist “footing”, a low dielectric constant, and high degrees of adhesion and hardness. Because nitrogen is not used in the deposition process (the carbon-dioxide-containing gas replaces nitrogen-containing gases in conventional processes), amines do not build into the deposited layer, thereby preventing photoresist “footing”.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: January 22, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: Patrick A. Van Cleemput, Ravi Kumar Laxman, Jen Shu, Michelle T. Schulberg, Bunsen Nie
  • Patent number: 6258653
    Abstract: A method of making a capacitor on a conductive surface, preferably on a polysilicon surface includes contamination cleaning the surface with a high density plasma (HDP) of a first gaseous agent, such as hydrogen, then growing a silicon nitride barrier layer on the surface using a high density plasma (HDP) of nitrogen. A layer of tantalum oxide is then deposited on the silicon nitride layer to form a capacitor dielectric layer. A second silicon nitride layer is then grown on the capacitor dielectric layer, also using an HDP nitrogen plasma with the addition of a silicon containing gas, such as silane. Finally, a conductive layer is deposited on the second silicon nitride layer to form the capacitor. The HDP plasma is heated using an inductively coupled radio frequency generator. The invention also includes a capacitor constructed on a conductive surface by the method of the invention.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: July 10, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Kok Heng Chew, Patrick van Cleemput, Kathy Konjuh, Tirunelveli Subramaniam Ravi
  • Patent number: 6225169
    Abstract: A method of constructing a gate dielectric on a semiconductor surface includes cleaning a silicon surface then growing a silicon nitride barrier layer on the silicon surface using a high density plasma (HDP) of nitrogen. A gate dielectric layer is then deposited on the silicon nitride layer and a second silicon nitride layer is then grown on the dielectric layer, also using an HDP nitrogen plasma, followed by deposition of the conductive gate layer. The HDP nitrogen plasma is heated using an inductively coupled radio frequency generator. The invention also includes a gated device including a gate dielectric constructed on a semiconductor surface by the method of the invention.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: May 1, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Kok Heng Chew, Patrick van Cleemput
  • Patent number: 6149779
    Abstract: A low dielectric constant gap-fill process using high density plasma (HDP) deposition is provided for depositing a boron-doped silicon oxide layer to eliminate the damaging effects of fluorine on underlying circuitry while still maintaining a low dielectric constant for an intermetal dielectric (IMD) layer.
    Type: Grant
    Filed: November 3, 1998
    Date of Patent: November 21, 2000
    Assignee: Novellus Systems, Inc.
    Inventor: Patrick A. Van Cleemput
  • Patent number: 6030881
    Abstract: A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and etch steps having varying etch rate-to-deposition rate (etch/dep) ratios. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses an etch/dep ratio greater than one to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: February 29, 2000
    Assignees: Novellus Systems, Inc., International Business Machines Corporation
    Inventors: George D. Papasouliotis, Ashima B. Chakravarti, Richard A. Conti, Laertis Economikos, Patrick A. Van Cleemput
  • Patent number: 5872058
    Abstract: A process for filling high aspect ratio gaps on substrates uses conventional high density plasma deposition processes while reducing the concentration of the inert gas, such as Ar, to 0-13% of the total process gas flow. By reducing the inert gas concentration, sputtering or etching is reduced, resulting in reduced sidewall deposition from the sputtered material. Consequently, gaps with aspect ratios of 3.0:1 and higher can be filled without the formation of voids and without damaging circuit elements.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: February 16, 1999
    Assignee: Novellus Systems, Inc.
    Inventors: Patrick A. Van Cleemput, Thomas W. Mountsier