Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

Abstract: A substrate for applications in the fields of radiofrequency electronics and microelectronics, comprises: a base substrate; a single carbon layer positioned on and directly in contact with the base substrate, with the carbon layer having a thickness ranging from 1 nm to 5 nm; an insulator layer positioned on the carbon layer; and a device layer positioned on the insulator layer.

Abstract: Production of a device for connecting a nano-object to an external electrical system (SEE) including: a first chip provided with conducting areas (8a, 8b) and a first nano-object (50) connected to the conducting areas, the first chip being assembled on a support (70) such that the first nano-object is arranged facing an upper face of the support, the device being further provided with first connection elements (80a, 80b) capable of being connected to the external electrical system and arranged on and in contact with the first conducting areas (8a, 8b), the first connection elements being formed on the side of the upper face of the support (70) and being accessible from the side of the upper face of the support.

Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

Abstract: Manufacturing of a device to connect at least one nano-object to an external electrical system, comprising a support provided with a semiconducting layer in which the first doped zones are formed at a spacing from each other, an external electrical system being connectable to the first doped zones, each first doped zone (8a, 8b) being in contact with a second doped zone on which a portion of the nano-object is located, the second doped zones being separated from each other and with a thickness less than the thickness of the first doped zones.

Abstract: An electronic device for measuring at least one electrical characteristic of an object, including a supporting base provided with at least two measuring units each including at least two sets of electrodes including electrodes, is provided. The electrodes of the sets of electrodes of the same measuring unit are interdigitated such that each electrode of one of the sets of electrodes of the measuring unit is spaced by an inter-electrode distance from an electrode, of the other of the sets of electrodes of the measuring unit, which is adjacent thereto, the electrodes differ in the features in respect of contact with the object and/or the electrode spacing thereof so as to make a differential current measurement.

Abstract: Manufacturing of a device to connect at least one nano-object to an external electrical system, comprising a support provided with a semiconducting layer (4) in which the first doped zones (8a, 8b) are formed at a spacing from each other, an external electrical system (SEE) being connectable to the first doped zones, each first doped zone (8a, 8b) being in contact with a second doped zone (12a, 12b) on which a portion of the nano-object is located, the second doped zones (12a, 12b) being separated from each other and with a thickness (e2) less than the thickness (e1) of the first doped zones (FIG. 1).

Abstract: The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor-on-insulator type structures including carrying out the test on a sample structure from the batch.

Abstract: A method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950° C. and less than 1200° C.

Abstract: Production of a device for connecting a nano-object to an external electrical system (SEE) including: a first chip provided with conducting areas (8a, 8b) and a first nano-object (50) connected to the conducting areas, the first chip being assembled on a support (70) such that the first nano-object is arranged facing an upper face of the support, the device being further provided with first connection elements (80a, 80b) capable of being connected to the external electrical system and arranged on and in contact with the first conducting areas (8a, 8b), the first connection elements being formed on the side of the upper face of the support (70) and being accessible from the side of the upper face of the support.

Abstract: An electronic device for measuring at least one electrical characteristic of an object, including a supporting base provided with at least two measuring units each including at least two sets of electrodes including electrodes, is provided. The electrodes of the sets of electrodes of the same measuring unit are interdigitated such that each electrode of one of the sets of electrodes of the measuring unit is spaced by an inter-electrode distance from an electrode, of the other of the sets of electrodes of the measuring unit, which is adjacent thereto, the electrodes differ in the features in respect of contact with the object and/or the electrode spacing thereof so as to make a differential current measurement.

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract: A method for measuring defects in a silicon substrate obtained by silicon ingot pulling, wherein the defects have a size of less than 20 nm. The method includes applying a first defect consolidation heat treatment to the substrate at a temperature of between 750° C. and 850° C. for a time period of between 30 minutes and 1 hour to consolidate the defects; applying a second defect enlargement heat treatment to the substrate at a temperature of between 900° C. and 1000° C. for a time period of between 1 hour and 10 hour hours to enlarge the defects to a size of greater than or equal to 20 nm, with the enlarged defects containing oxygen precipitates; measuring size and density of the enlarged defects in a surface layer of the substrate; and calculating the initial size of the defects on the basis of the measurements of the enlarged defects.

Abstract: This method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950° C. and less than 1200° C.

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract: A method to thin an initial silicon-on-insulator substrate that has a layer of silicon oxide buried between a silicon carrier substrate and a silicon surface layer.

Abstract: The invention concerns a method of testing a semiconductor on insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor on insulator type structures including carrying out the test on a sample structure from the batch.

Abstract: The ancillary tool according to the invention comprises a handle for manipulating an acetabulum provided, in its distal part, with a head for gripping the acetabulum and, in its proximal part, with a surface for application of a force of impaction. The tool further comprises at least one added endpiece adapted to be removably connected to the distal end of the handle. This endpiece defines both a face for wedging the acetabulum and an opposite face for interaction of the endpiece with the head of the handle, these faces both being borne by a radially deformable supple ring. The invention is particularly applicable to the positioning of an acetabular prosthesis in an anatomical or prosthetic cavity of a patient's hip.