Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.

Abstract: A method for measuring defects in a silicon substrate obtained by silicon ingot pulling, wherein the defects have a size of less than 20 nm. The method includes applying a first defect consolidation heat treatment to the substrate at a temperature of between 750 and 850° C. for a time of between 30 minutes and 1 hour to consolidate the defects; applying a second defect enlargement heat treatment to the substrate at a temperature of between 900 and 1000° C. for a time of between 1 hour and 10 hour to enlarge the defects to a size of greater than or equal to 20 nm, with the enlarged defects containing oxygen precipitates; measuring size and density of the enlarged defects in a surface layer of the substrate; and calculating the initial size of the defects on the basis of the measurements of the enlarged defects.

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract: A method for controlling the distribution of the stresses in a structure of the semiconductor-on-insulator type during its manufacturing, which includes a thin layer of semiconducting material on a supporting substrate and an insulating layer present on each of the front and rear faces of the supporting substrate, with the insulating layer on the front face forming at least one portion of a thick buried insulator (BOX) layer. The method includes the adhesive bonding of the thin layer onto the supporting substrate. Prior to this adhesive bonding, the insulating layer on the rear face of the supporting substrate is covered with a distinct material that is capable of withstanding deoxidation. The covering material, in combination with this insulating layer on the rear face of the supporting substrate, at least partly compensates for the stress exerted by the buried insulator (BOX) on the supporting substrate.

Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.

Abstract: The invention concerns a method to thin an initial silicon-on-insulator substrate that has a layer of silicon oxide buried between a silicon carrier substrate and a silicon surface layer.

Abstract: The present invention provides improved methods for fabricating compound-material wafers, in particular a silicon on insulator type wafer. The improved methods lead to reduced numbers of deflects arising on or near the periphery of the wafers. In a first method, wafers are selected in dependence on edge roll off values determined at about 0.5-2.5 mm away from the edge of the wafer, where edge roll off values are determined in dependence on the second derivative of the wafer height profiles. In a second method, wafers selected according to the first method are further processed by bonding, forming a splitting layer, and detaching the two wafers at the splitting layer.

Abstract: A method for forming a semiconductor structure that includes a thin layer of semiconductor material on a receiver wafer is disclosed. The method includes removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the epitaxial layer from the donor wafer to the receiver wafer. The thickness removed during the surface preparation is adapted to enable formation of a new semiconductor structure from the remaining epitaxial portion of the donor wafer.

Abstract: The invention relates to a method for manufacturing compound material wafers, in particular, silicon on insulator type wafers, by providing an initial donor substrate, forming an insulating layer over the initial donor substrate, forming a predetermined splitting area in the initial donor substrate, attaching the initial donor substrate onto a handle substrate and detaching the donor substrate at the predetermined splitting area, thereby transferring a layer of the initial donor substrate onto the handle substrate to form a compound material wafer. In order to be able to reuse the donor substrate more often, the invention proposes to carry out the thermal treatment step to form the insulating layer at a temperature of less than 950° C., in particular, less than 900° C., and preferably at 850° C. The invention also relates to a silicon on insulator type wafer manufactured according to the inventive method.

Abstract: A method of planarization of a surface of a heteroepitaxial layer by chemical-mechanical polishing the disturbed surface of the heteroepitaxial layer with a polishing pad having a compressibility greater than 2% and less than 15% and a slurry comprising at least 20% of silica particles having an average diameter between about 70 and about 100 nm. This method allows to reach high polishing rates appropriated for eliminating surface defects on heteroepitaxial layers, such as crosshatch patterns, and to achieve, in the same time, a final polish that is desirable to facilitate further operations.

Abstract: A method for forming a semiconductor structure that includes a thin layer of semiconductor material on a receiver wafer is disclosed. The method includes removing a thickness of material from a donor wafer, which comprises a support substrate and an epitaxial layer, for surface preparation and transferring a portion of the epitaxial layer from the donor wafer to the receiver wafer. The thickness removed during the surface preparation is adapted to enable formation of a new semiconductor structure from the remaining epitaxial portion of the donor wafer.

Abstract: The invention relates to methods for manufacturing compound material wafers, in particular silicon on insulator wafers, by the steps of providing a donor substrate, forming an insulating layer, providing a handle substrate, creating a predetermined splitting area in the donor substrate, attaching the donor substrate to the handle substrate and detaching at the predetermined splitting area to achieve the compound material wafer. In order to be able to more often reuse the remainder of the donor substrate in subsequent manufacturing runs, various embodiments are disclosed, such as the insulating layer can be provided on the donor substrate at a maximum thickness of 500 A, or that the insulating layer can be provided by deposition or only upon the handle substrate. Alternatively, no insulating layer is provided so that the donor and handle substrates can have different crystal orientations.

Abstract: The ancillary tool according to the invention comprises a handle for manipulating an acetabulum provided, in its distal part, with a head for gripping the acetabulum and, in its proximal part, with a surface for application of a force of impaction. The tool further comprises at least one added endpiece adapted to be removably connected to the distal end of the handle. This endpiece defines both a face for wedging the acetabulum and an opposite face for interaction of the endpiece with the head of the handle, these faces both being borne by a radially deformable supple ring. The invention is particularly applicable to the positioning of an acetabular prosthesis in an anatomical or prosthetic cavity of a patient's hip.

Abstract: This invention provides methods for predictively revealing, in bulk silicon substrates, latent crystalline defects in bulk silicon substrates that become apparent only after subsequent processing, e.g., after processing during which multiple layers are split and lifted from the bulk substrates. Preferred predictive methods include a revealing heat treatment of bulk substrates conducted in a non-reducing atmosphere at a temperature in the range from approximately 500° C. to 1300° C. If desired, a further revealing heat treatment or defect enlargement step can be performed to enlarge defects revealed by the first revealing heat treatment.

Abstract: This invention provides methods for manufacturing compound-material wafers and methods for recycling donor substrates that results from manufacturing compound-material wafers. The provided methods includes at least one further thermal treatment step configured to at least partially reduce oxygen precipitates and/or nuclei. Reduction of oxygen precipitates and/or nuclei, improves the recycling rate of the donor substrate.

Abstract: The invention relates to a method for manufacturing compound material wafers, in particular, silicon on insulator type wafers, by providing an initial donor substrate, forming an insulating layer over the initial donor substrate, forming a predetermined splitting area in the initial donor substrate, attaching the initial donor substrate onto a handle substrate and detaching the donor substrate at the predetermined splitting area, thereby transferring a layer of the initial donor substrate onto the handle substrate to form a compound material wafer. In order to be able to reuse the donor substrate more often, the invention proposes to carry out the thermal treatment step to form the insulating layer at a temperature of less than 950° C., in particular, less than 900° C., and preferably at 850° C. The invention also relates to a silicon on insulator type wafer manufactured according to the inventive method.

Abstract: An ancillary tool and method for manipulating and implanting a prosthetic acetabulum including a tool provided, adjacent a distal part, with a head for interacting with an endpiece that is used for gripping the acetabulum and, in its proximal part, with a surface for application of a force along the handle. The endpiece is preferably removably connected to the distal end of the handle. The endpiece includes an elastically deformable ring having an outer face for expanding radially outwardly to initially grip the acetabulum and an opposite face for interaction with the head of the handle, such that upon a force being applied to drive the head into a cavity of the endpiece, the ring is radially expanded to expand the acetabulum in place after which the ring elastically returns to its original shape as the head is removed from the cavity.

Abstract: This invention provides methods for predictively revealing, in bulk silicon substrates, latent crystalline defects in bulk silicon substrates that become apparent only after subsequent processing, e.g., after processing during which multiple layers are split and lifted from the bulk substrates. Preferred predictive methods include a revealing heat treatment of bulk substrates conducted in a non-reducing atmosphere at a temperature in the range from approximately 500° C. to 1300° C. If desired, a further revealing heat treatment or defect enlargement step can be performed to enlarge defects revealed by the first revealing heat treatment.