Patents by Inventor Paul C. Parries
Paul C. Parries has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9484269Abstract: Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.Type: GrantFiled: June 24, 2010Date of Patent: November 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Joseph Ervin, Jeffrey B. Johnson, Kevin McStay, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
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Patent number: 9311443Abstract: Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed.Type: GrantFiled: June 17, 2014Date of Patent: April 12, 2016Inventors: Dureseti Chidambarrao, James A. Culp, Paul C. Parries, Ian P. Stobert
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Patent number: 9240482Abstract: A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.Type: GrantFiled: September 4, 2014Date of Patent: January 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Ravi K. Dasaka, Shreesh Narasimha, Ahmed Nayaz Noemaun, Karen A. Nummy, Katsunori Onishi, Paul C. Parries, Chengwen Pei, Geng Wang, Bidan Zhang
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Publication number: 20150363536Abstract: Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed.Type: ApplicationFiled: June 17, 2014Publication date: December 17, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dureseti Chidambarrao, James A. Culp, Paul C. Parries, Ian P. Stobert
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Publication number: 20150348974Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.Type: ApplicationFiled: August 7, 2015Publication date: December 3, 2015Inventors: Shreesh Narasimha, Katsunori Onishi, Paul C. Parries, Chengwen Pei, Geng Wang
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Publication number: 20150349121Abstract: A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.Type: ApplicationFiled: September 4, 2014Publication date: December 3, 2015Inventors: Ravi K. Dasaka, Shreesh Narasimha, Ahmed Nayaz Noemaun, Karen A. Nummy, Katsunori Onishi, Paul C. Parries, Chengwen Pei, Geng Wang, Bidan Zhang
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Publication number: 20150348972Abstract: A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. The asymmetric stressor enables low leakage current for the body region during charge storage while the drain voltage is low, and enables a body potential coupled to the drain region and a lower threshold voltage for the access transistor during read and write operations.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shreesh Narasimha, Katsunori Onishi, Paul C. Parries, Chengwen Pei, Geng Wang
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Patent number: 9136321Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.Type: GrantFiled: April 30, 2014Date of Patent: September 15, 2015Assignee: International Business Machines CorporationInventors: Shreesh Narasimha, Katsunori Onishi, Paul C. Parries, Chengwen Pei, Geng Wang
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Patent number: 9087927Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.Type: GrantFiled: October 23, 2014Date of Patent: July 21, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-jung Kwon, Paul C. Parries, Hongwen Yan
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Patent number: 8963283Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: GrantFiled: March 31, 2014Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
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Publication number: 20150044853Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.Type: ApplicationFiled: October 23, 2014Publication date: February 12, 2015Inventors: Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-jung Kwon, Paul C. Parries, Hongwen Yan
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Publication number: 20150037941Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled with a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A portion of the upper pad layer is removed to define a line cavity. A fin-defining spacer comprising a material different from the material of the dielectric capacitor cap and the upper pad layer is formed around the line cavity by deposition of a conformal layer and an anisotropic etch. The upper pad layer is removed, and the fin-defining spacer is employed as an etch mask to form a semiconductor fin that laterally contacts the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.Type: ApplicationFiled: October 17, 2014Publication date: February 5, 2015Inventors: Josephine B. Chang, Babar A. Khan, Paul C. Parries, Xinhui Wang
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Patent number: 8940617Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: GrantFiled: November 21, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
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Patent number: 8901706Abstract: A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.Type: GrantFiled: January 6, 2012Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Michael P. Chudzik, Bachir Dirahoui, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-jung Kwon, Paul C. Parries, Hongwen Yan
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Patent number: 8835994Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.Type: GrantFiled: June 1, 2010Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
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Publication number: 20140210039Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oh-Jung KWON, Junedong LEE, Paul C. PARRIES, Dominic J. SCHEPIS
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Patent number: 8741780Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.Type: GrantFiled: March 12, 2013Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
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Patent number: 8723243Abstract: A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.Type: GrantFiled: November 4, 2013Date of Patent: May 13, 2014Assignee: International Business Machines CorporationInventors: Brian W. Messenger, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
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Patent number: 8716776Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: GrantFiled: June 26, 2012Date of Patent: May 6, 2014Assignee: International Business Machines CorporationInventors: Oh-Jung Kwon, Junedong Lee, Paul C. Parries, Dominic J. Schepis
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Publication number: 20140080281Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: ApplicationFiled: November 21, 2013Publication date: March 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oh-Jung KWON, Junedong LEE, Paul C. PARRIES, Dominic J. SCHEPIS