Patents by Inventor Paul C. Parries
Paul C. Parries has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120122303Abstract: Disclosed is a method of forming a semiconductor device structure in a semiconductor layer. The method includes forming a first trench of a first width and a second trench of a second width in the semiconductor layer; depositing a layer of first material which conforms to a wall of the first trench but does not fill it and which fills the second trench; removing the first material from the first trench, the first material remaining in the second trench; depositing a second material into and filling the first trench and over a top of the first material in the second trench; and uniformly removing the second material from the top of the first material in the second trench, wherein the first trench is filled with the second material and the second trench is filled with the first material and wherein the first material is different from the second material.Type: ApplicationFiled: November 11, 2010Publication date: May 17, 2012Applicant: International Business Machines CorporationInventors: PAUL C. PARRIES, Yanli Zhang
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Publication number: 20120086077Abstract: An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.Type: ApplicationFiled: October 7, 2010Publication date: April 12, 2012Applicant: International Business Machines CorporationInventors: DAVID M FRIED, Jeffrey B. Johnson, Kevin McStay, Paul C. Parries, Chengwen Pei, Gan Wang, Geng Wang, Yanli Zhang
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Publication number: 20120049295Abstract: The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer.Type: ApplicationFiled: August 24, 2010Publication date: March 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Geng Wang, Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries
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Publication number: 20120012971Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.Type: ApplicationFiled: July 19, 2010Publication date: January 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oh-Jung KWON, Junedong LEE, Paul C. PARRIES, Dominic J. SCHEPIS
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Publication number: 20110316061Abstract: Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph ERVIN, Jeffrey B. JOHNSON, Kevin MCSTAY, Paul C. PARRIES, Chengwen PEI, Geng WANG, Yanli ZHANG
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Publication number: 20110291169Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.Type: ApplicationFiled: June 1, 2010Publication date: December 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
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Publication number: 20110193193Abstract: A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.Type: ApplicationFiled: February 11, 2010Publication date: August 11, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Abhishek Dube, Subramanian S. Iyer, Babar Ali Khan, Oh-jung Kwon, Junedong Lee, Paul C. Parries, Chengwen Pei, Gerd Pfeiffer, Ravi M. Todi, Geng Wang
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Publication number: 20110092043Abstract: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.Type: ApplicationFiled: December 21, 2010Publication date: April 21, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MaryJane Brodsky, Kangguo Cheng, Herbert L. Ho, Paul C. Parries, Kevin R. Winstel
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Patent number: 7923815Abstract: By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm?3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.Type: GrantFiled: January 7, 2008Date of Patent: April 12, 2011Assignee: International Business Machines CorporationInventors: Geng Wang, Kangguo Cheng, Johnathan E. Faltermeier, Paul C. Parries
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Patent number: 7888723Abstract: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.Type: GrantFiled: January 18, 2008Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Kangguo Cheng, Herbert L. Ho, Paul C. Parries, Kevin R. Winstel
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Publication number: 20100237417Abstract: The present invention, provides a semiconductor device including a substrate including a semiconductor layer overlying an insulating layer, wherein a back gate structure is present underlying the insulating layer and a front gate structure on the semiconductor layer; a channel dopant region underlying the front gate structure of the substrate, wherein the channel dopant region has a first concentration present at an interface of the semiconductor layer and the insulating layer and at least a second concentration present at the interface of the front gate structure and the semiconductor layer, wherein the first concentration is greater than the second concentration; and a source region and drain region present in the semiconductor layer of the substrate.Type: ApplicationFiled: February 8, 2010Publication date: September 23, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Geng Wang, Paul C. Parries
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Patent number: 7791124Abstract: A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.Type: GrantFiled: May 21, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Herbert L. Ho, Paul C. Parries, Geng Wang
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Patent number: 7705386Abstract: A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.Type: GrantFiled: January 7, 2008Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Johnathan E. Faltermeier, Herbert L. Ho, Paul C. Parries
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Publication number: 20090289291Abstract: A bottle shaped trench for an SOI capacitor is formed by a simple processing sequence. A non-conformal dielectric layer with an optional conformal dielectric diffusion barrier layer underneath is formed on sidewalls of a deep trench. Employing an isotropic etch, the non-conformal dielectric layer is removed from a bottom portion of the deep trench, leaving a dielectric spacer covering sidewalls of the buried insulator layer and the top semiconductor layer. The bottom portion of the deep trench is expanded to form a bottle shaped trench, and a buried plated is formed underneath the buried insulator layer. The dielectric spacer may be recessed during formation of a buried strap to form a graded thickness dielectric collar around the upper portion of an inner electrode. Alternately, the dielectric spacer may be removed prior to formation of a buried strap.Type: ApplicationFiled: May 21, 2008Publication date: November 26, 2009Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Herbert L. Ho, Paul C. Parries, Geng Wang
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Publication number: 20090240875Abstract: Disclosed are embodiments of memory circuit having two discrete memory devices with two discrete memory arrays that store essentially identical data banks. The first device is a conventional memory adapted to perform all maintenance operations that require read functions (i.e., all update and refresh operations). The second device is a DRAM-based CAM device adapted to perform parallel search and overwrite operations only. Performance of overwrite operations by the second device occurs in conjunction with performance of maintenance operations by the first device so that corresponding memory cells in the two devices store essentially identical data values. Since the data banks in the memory devices are essentially identical and since maintenance and parallel search operations are not performed by the same device, the parallel search operations can be performed without interruption. Also disclosed are embodiments of an associated design structure and method.Type: ApplicationFiled: March 18, 2008Publication date: September 24, 2009Inventors: Albert M. Chu, Paul C. Parries, Daryl M. Seitzer
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Publication number: 20090184356Abstract: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.Type: ApplicationFiled: January 18, 2008Publication date: July 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MaryJane Brodsky, Kangguo Cheng, Herbert L. Ho, Paul C. Parries, Kevin R. Winstel
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Patent number: 7564729Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.Type: GrantFiled: March 27, 2008Date of Patent: July 21, 2009Assignee: International Business Machines CorporationInventors: John Edward Barth, Jr., Paul C. Parries, William Robert Reohr, Matthew R. Wordeman
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Publication number: 20090173980Abstract: A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.Type: ApplicationFiled: January 7, 2008Publication date: July 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Johnathan E. Faltermeier, Herbert L. Ho, Paul C. Parries
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Publication number: 20090174031Abstract: By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm?3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.Type: ApplicationFiled: January 7, 2008Publication date: July 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Geng Wang, Kangguo Cheng, Johnathan E. Faltermeier, Paul C. Parries
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Publication number: 20080175085Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.Type: ApplicationFiled: March 27, 2008Publication date: July 24, 2008Applicant: International Business Machines CorporationInventors: John Edward Barth, Paul C. Parries, William Robert Reohr, Matthew R. Wordeman