Patents by Inventor Paul C. Parries
Paul C. Parries has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7382672Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.Type: GrantFiled: May 29, 2007Date of Patent: June 3, 2008Assignee: International business Machines CorporationInventors: John Edward Barth, Jr., Paul C. Parries, William Robert Reohr, Matthew R. Wordeman
-
Publication number: 20070267671Abstract: A trench capacitor and related methods are disclosed including a trench having lateral extensions extending in only one direction from the trench filled with a capacitor material. In one embodiment, the trench capacitor includes a trench within a substrate, and at least one lateral extension extending from the trench in only one direction, wherein the trench and each lateral extension are filled with a capacitor material. The lateral extensions increase surface area for the trench capacitor, but do not take up as much space as conventional structures.Type: ApplicationFiled: May 17, 2006Publication date: November 22, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Lisa F. Edge, Johnathan E. Faltermeier, Paul C. Parries, William C. Wille
-
Patent number: 7286385Abstract: A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit.Type: GrantFiled: July 27, 2005Date of Patent: October 23, 2007Assignee: International Business Machines CorporationInventors: John Edward Barth, Jr., Paul C. Parries, William Robert Reohr, Matthew R. Wordeman
-
Patent number: 7193262Abstract: A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.Type: GrantFiled: December 15, 2004Date of Patent: March 20, 2007Assignee: International Business Machines CorporationInventors: Herbert L. Ho, John E. Barth, Jr., Ramachandra Divakaruni, Wayne F. Ellis, Johnathan E. Faltermeier, Brent A. Anderson, Subramanian S. Iyer, Deok-Kee Kim, Randy W. Mann, Paul C. Parries
-
Patent number: 7194670Abstract: Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate ānā sets of CAD information which are then time-multiplexed to the embedded memory at a speed ānā times faster than the BIST operating speed.Type: GrantFiled: February 13, 2004Date of Patent: March 20, 2007Assignee: International Business Machines Corp.Inventors: Jonathan R. Fales, Gregory J. Fredeman, Kevin W. Gorman, Mark D. Jacunski, Toshiaki Kirihata, Alan D. Norris, Paul C. Parries, Matthew R. Wordeman
-
Patent number: 7078756Abstract: The present invention provides collarless trench semiconductor memory devices having minimized vertical parasitic FET leakage and methods of forming the same.Type: GrantFiled: December 6, 2004Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Yoichi Otani, Herbert L. Ho, Babar A. Khan, Paul C. Parries
-
Patent number: 7057866Abstract: An integrated circuit system having a plurality of macros is provided. The integrated circuit system includes an external voltage supply input configured for supplying an external voltage to the integrated circuit; and a plurality of internal voltage supply generators, each of the plurality of internal voltage supply generators being connected to a respective macro of the plurality of macros and configured for receiving the external voltage via the external voltage supply input for generating an internal voltage supply for operating its respective macro. Each of the plurality of internal voltage supply generators includes circuitry for generating the internal voltage supply and circuitry for disconnecting at least a portion of its respective macro. The integrated circuit system can be applied to a semiconductor chip to save active or stand-by power. It can also be used to disconnect a defective portion of the chip and optionally replace it with a non-defective portion of the chip.Type: GrantFiled: August 14, 2001Date of Patent: June 6, 2006Assignee: International Business Machines Corp.Inventors: Louis L. Hsu, Rajiv V. Joshi, Chorng-Lii Hwang, Toshiaki K. Kirihata, Paul C. Parries
-
Patent number: 7046572Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.Type: GrantFiled: June 16, 2003Date of Patent: May 16, 2006Assignee: International Business Machines CorporationInventors: David R. Hansen, Gregory J. Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
-
Patent number: 7023758Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.Type: GrantFiled: August 17, 2005Date of Patent: April 4, 2006Assignee: International Business Machines CorporationInventors: David R. Hanson, Gregory J Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
-
Patent number: 6967885Abstract: A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.Type: GrantFiled: January 15, 2004Date of Patent: November 22, 2005Assignee: International Business Machines CorporationInventors: John E. Barth, Jr., Toshiaki Kirihata, Paul C. Parries
-
Publication number: 20040252573Abstract: A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.Type: ApplicationFiled: June 16, 2003Publication date: December 16, 2004Applicant: International Business Machine CorporationInventors: David R. Hanson, Gregory J. Fredeman, John W. Golz, Hoki Kim, Paul C. Parries
-
Patent number: 6760240Abstract: A method and structure for an array of content addressable memory (CAM) cells is disclosed. Each of the CAM cells has a search line and a bitline parallel to the search line. Across the array, search lines and bit lines of the CAM cells are interdigitated so that the search lines and bitlines alternate across the array. CAM cell macro's are inverted with respect to adjacent macros to balance parasitic capacitances across the array.Type: GrantFiled: November 22, 2002Date of Patent: July 6, 2004Assignee: International Business Machines CorporationInventors: Robert E. Busch, Albert M. Chu, Ezra D. B. Hall, Paul C. Parries, Daryl M. Seizter
-
Publication number: 20040100830Abstract: A method and structure for an array of content addressable memory (CAM) cells is disclosed. Each of the CAM cells has a search line and a bitline parallel to the search line. Across the array, search lines and bit lines of the CAM cells are interdigitated so that the search lines and bitlines alternate across the array. CAM cell macro's are inverted with respect to adjacent macros to balance parasitic capacitances across the array.Type: ApplicationFiled: November 22, 2002Publication date: May 27, 2004Applicant: International Business Machines CorporationInventors: Robert E. Busch, Albert M. Chu, Ezra D. B. Hall, Paul C. Parries, Daryl M. Seizter
-
Publication number: 20030034825Abstract: An integrated circuit system having a plurality of macros is provided. The integrated circuit system includes an external voltage supply input configured for supplying an external voltage to the integrated circuit; and a plurality of internal voltage supply generators, each of the plurality of internal voltage supply generators being connected to a respective macro of the plurality of macros and configured for receiving the external voltage via the external voltage supply input for generating an internal voltage supply for operating its respective macro. Each of the plurality of internal voltage supply generators includes circuitry for generating the internal voltage supply and circuitry for disconnecting at least a portion of its respective macro. The integrated circuit system can be applied to a semiconductor chip to save active or stand-by power. It can also be used to disconnect a defective portion of the chip and optionally replace it with a non-defective portion of the chip.Type: ApplicationFiled: August 14, 2001Publication date: February 20, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis L. Hsu, Rajiv V. Joshi, Chorng-Lii Hwang, Toshiaki K. Kirihata, Paul C. Parries
-
Patent number: 6518145Abstract: A method of manufacturing a semiconductor trench device comprises forming a dielectric on a substrate, the dielectric having an underlying oxide layer adjacent the substrate, etching a trench in the dielectric and the substrate, forming a recess in the underlying oxide layer, filling the recess with a nitride plug, filling the trench a conductive material and oxidizing the dielectric and the conductive material, wherein the nitride plug controls a shape of a corner of the trench.Type: GrantFiled: August 6, 1998Date of Patent: February 11, 2003Assignees: International Business Machines Corporation, Siemens AktiengesellschaftInventors: Johann Alsmeier, George R. Goth, Max G. Levy, Victor R. Nastasi, James A. O'Neill, Paul C. Parries
-
Publication number: 20020137300Abstract: A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.Type: ApplicationFiled: May 22, 2002Publication date: September 26, 2002Applicant: International Business Machines CorporationInventors: Ricky S. Amos, Arne W. Ballantine, Gregory Bazan, Bomy A. Chen, Douglas D. Coolbaugh, Ramachandra Divakaruni, Heidi L. Greer, Herbert L. Ho, Joseph F. Kudlacik, Bernard P. Leroy, Paul C. Parries, Gary L. Patton
-
Patent number: 6429101Abstract: A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.Type: GrantFiled: January 29, 1999Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Arne W. Ballantine, Gregory Bazan, Bomy A. Chen, Douglas D. Coolbaugh, Ramachandra Divakaruni, Heidi L. Greer, Herbert L. Ho, Joseph F. Kudlacik, Bernard P. Leroy, Paul C. Parries, Gary L. Patton
-
Patent number: 6410399Abstract: A semiconductor device manufacturing method for silicidizing silicon-containing areas in array regions of dynamic random access memory (DRAMS)and embedded DRAM (eDRAM) devices to lower electrical resistance, and improve device reliability at low temperatures.Type: GrantFiled: June 29, 2000Date of Patent: June 25, 2002Assignee: International Business Machines CorporationInventors: Philip Lee Flaitz, Herbert L. Ho, Subramanian Iyer, Babar Khan, Paul C. Parries
-
Publication number: 20020005533Abstract: A DRAM semiconductor device wherein a substrate plate trench (SPT) memory cell is formed in an N−-type substrate, without an epitaxial layer in which the substrate is biased at circuit ground in order to ensure that the substrate surrounding the trench capacitors is biased into accumulation in order to avoid unacceptable loss of storage node capacitance which would be caused by allowing the substrate to go into depletion.Type: ApplicationFiled: December 30, 1998Publication date: January 17, 2002Inventors: DONALD M. KENNEY, PAUL C. PARRIES
-
Patent number: 6294449Abstract: A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.Type: GrantFiled: November 23, 1999Date of Patent: September 25, 2001Assignee: International Business Machines CorporationInventors: Teresa J. Wu, Bomy A. Chen, John W. Golz, Charles W. Koburger, III, Paul C. Parries, Christopher J. Waskiewicz, Jin Jwang Wu