Patents by Inventor Paul Chow
Paul Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10685630Abstract: According to various aspects, just-in-time system bandwidth changes may be implemented in hardware to optimize power consumption and performance in an electronic device. More particularly, in a periodic system associated with an electronic device, a bandwidth for a next frame may be configured during a current frame via software operating on the electronic device. Hardware associated with the periodic system may issue a bandwidth change request for the next frame when a current time reaches a bandwidth increase threshold in response to actual processing time associated with the current frame finishing prior to the bandwidth increase threshold, which may be defined relative to a timer deadline that defines when the next frame starts to process.Type: GrantFiled: June 8, 2018Date of Patent: June 16, 2020Assignee: QUALCOMM IncorporatedInventors: Carlos Javier Moreira, Paul Chow, Dhaval Kanubhai Patel
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Publication number: 20190378478Abstract: According to various aspects, just-in-time system bandwidth changes may be implemented in hardware to optimize power consumption and performance in an electronic device. More particularly, in a periodic system associated with an electronic device, a bandwidth for a next frame may be configured during a current frame via software operating on the electronic device. Hardware associated with the periodic system may issue a bandwidth change request for the next frame when a current time reaches a bandwidth increase threshold in response to actual processing time associated with the current frame finishing prior to the bandwidth increase threshold, which may be defined relative to a timer deadline that defines when the next frame starts to process.Type: ApplicationFiled: June 8, 2018Publication date: December 12, 2019Inventors: Carlos Javier MOREIRA, Paul CHOW, Dhaval Kanubhai PATEL
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Patent number: 10445902Abstract: Techniques are described in which a device is configured to retrieve a metadata buffer for rendering a sub-frame of a set of sub-frames for a frame. A data block of a data buffer is configured to store image data for rendering the sub-frame. In response to determining, based on the metadata buffer for rendering the sub-frame, that the sub-frame includes a color pattern, fixed color value, or combination thereof, the device refrains from retrieving the image data from the data block of the data buffer and determines the image data for rendering the sub-frame based on the metadata buffer.Type: GrantFiled: December 13, 2016Date of Patent: October 15, 2019Assignee: QUALCOMM IncorporatedInventors: Andrew Evan Gruber, Serag GadelRab, Zhenbiao Ma, Meghal Varia, Tao Wang, Tom Longo, Mark Sternberg, Paul Chow
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Publication number: 20180165789Abstract: Techniques are described in which a device is configured to retrieve a metadata buffer for rendering a sub-frame of a set of sub-frames for a frame. A data block of a data buffer is configured to store image data for rendering the sub-frame. In response to determining, based on the metadata buffer for rendering the sub-frame, that the sub-frame includes a color pattern, fixed color value, or combination thereof, the device refrains from retrieving the image data from the data block of the data buffer and determines the image data for rendering the sub-frame based on the metadata buffer.Type: ApplicationFiled: December 13, 2016Publication date: June 14, 2018Inventors: Andrew Evan Gruber, Serag GadelRab, Zhenbiao Ma, Meghal Varia, Tao Wang, Tom Longo, Mark Sternberg, Paul Chow
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Patent number: 9864647Abstract: A method and system for adjusting bandwidth within a portable computing device based on danger signals monitored from one on more elements of the portable computing device are disclosed. A danger level of an unacceptable deadline miss (“UDM”) element of the portable computing device may be determined with a danger level sensor within the UDM element. Next, a quality of service (“QoS”) controller may adjust a magnitude for one or more danger levels received based on the UDM element type that generated the danger level and based on a potential fault condition type associated with the particular danger level. The danger levels received from one UDM element may be mapped to at least one of another UDM element and a non-UDM element. A quality of service policy for each UDM element and non-UDM element may be mapped in accordance with the danger levels.Type: GrantFiled: January 2, 2015Date of Patent: January 9, 2018Assignee: QUALCOM IncorporatedInventors: Serag Gadelrab, Cristian Duroiu, Vinod Chamarty, Pooja Sinha, John Daniel Chaparro, Anil Vootukuru, Vinodh Ramesh Cuppu, Joseph Schweiray Lee, Vinay Mitter, Paul Chow, Ruolong Liu, Johnny Jone Wai Kuan
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Publication number: 20160127259Abstract: A method and system for managing safe downtime of shared resources within a portable computing device are described. The method may include determining a tolerance for a downtime period for an unacceptable deadline miss element of the portable computing device. Next, the determined tolerance for the downtime period may be transmitted to quality-of-service (“QoS”) controller. The QoS controller may determine if the tolerance for the downtime period needs to be adjusted. The QoS controller may receive a downtime request from one or more shared resources of the portable computing device. The QoS controller may determine if the downtime request needs to be adjusted. Next, the QoS controller may select a downtime request for execution and then identify which one or more unacceptable deadline miss elements of the portable computing device that are impacted by the selected downtime request.Type: ApplicationFiled: January 2, 2015Publication date: May 5, 2016Inventors: CRISTIAN DUROIU, VINOD CHAMARTY, SERAG GADELRAB, MICHAEL DROP, POOJA SINHA, RUOLONG LIU, JOHN DANIEL CHAPARRO, VINODH RAMESH CUPPU, JOSEPH SCHWEIRAY LEE, JOHNNY JONE WAI KUAN, PAUL CHOW, ANIL VOOTUKURU, VINAY MITTER
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Publication number: 20160117215Abstract: A method and system for adjusting bandwidth within a portable computing device based on danger signals monitored from one on more elements of the portable computing device are disclosed. A danger level of an unacceptable deadline miss (“UDM”) element of the portable computing device may be determined with a danger level sensor within the UDM element. Next, a quality of service (“QoS”) controller may adjust a magnitude for one or more danger levels received based on the UDM element type that generated the danger level and based on a potential fault condition type associated with the particular danger level. The danger levels received from one UDM element may be mapped to at least one of another UDM element and a non-UDM element. A quality of service policy for each UDM element and non-UDM element may be mapped in accordance with the danger levels.Type: ApplicationFiled: January 2, 2015Publication date: April 28, 2016Inventors: SERAG GADELRAB, CRISTIAN DUROIU, VINOD CHAMARTY, POOJA SINHA, JOHN DANIEL CHAPARRO, ANIL VOOTUKURU, VINODH RAMESH CUPPU, JOSEPH SCHWEIRAY LEE, VINAY MITTER, PAUL CHOW, RUOLONG LIU, JOHNNY JONE WAI KUAN
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Patent number: 8694570Abstract: A device and method for evaluating multidimensional discrete Fourier transforms (DFT) by eliminating transpose operations by transforming every dimension concurrently. At least one computing node is enabled to evaluate a DFT of one of a multidimensional input data set and a subgroup of the input data set, wherein the subgroup comprises groupings of elements taken from a plurality of selected dimensions of the input data set for subsequent multidimensional DFT operations.Type: GrantFiled: January 27, 2010Date of Patent: April 8, 2014Inventors: Arun Mohanlal Patel, Paul Chow
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Publication number: 20130159452Abstract: A memory server system is provided herein. It includes a first plurality of Field Programmable Gate Arrays (FPGA) application server nodes that are configured to parse the location of the FPGA data server nodes; a second plurality of FPGA data server nodes that are configured as memory controllers, each of the second plurality of FPGA data server nodes being connected to a plurality of RAM memory banks; and a network connection between the first plurality of FPGAs and the second plurality of FPGA processing nodes.Type: ApplicationFiled: December 3, 2012Publication date: June 20, 2013Inventors: Manuel Alejandro Saldana De Fuentes, Paul Chow
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Patent number: 8204106Abstract: The subject matter disclosed herein provides methods and apparatus, including computer program products, for providing intermediate compression or decompression for use with a video decoder and a memory. In one aspect, there is provided a method including receiving information to enable compression of a macroblock. At an intermediate section coupled to a video decoder and a memory, a macroblock may be compressed. The compression of the macroblock may be based on the received information. The compressed macroblock may be provided to memory. Related apparatus, systems, methods, and articles are also described.Type: GrantFiled: November 14, 2007Date of Patent: June 19, 2012Assignees: ATI Technologies, ULC, Advanced Micro Devices, Inc.Inventors: Greg Sadowski, Thomas E. Ryan, Daniel Wong, Paul Chow
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Patent number: 8106804Abstract: A video decoder (10) with reduced power consumption includes a power management controller (45) that is operative to select one of a plurality of different power consumption states for a video decoder (10), and, in response to the determination, vary power consumption of at least one operational portion of the video decoder (10). In addition, in one example, a method (200) for reducing power consumption for a video decoder (10) includes determining input stream encoding description data (34) to select one of a plurality of different power consumption states for a video decoder (10) and, in response to the determination, varying power consumption of at least one operational portion of the video decoder (10).Type: GrantFiled: August 24, 2010Date of Patent: January 31, 2012Assignee: ATI Technologies ULCInventors: Greg Sadowski, George Jacobs, Paul Chow
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Publication number: 20100322318Abstract: A video decoder (10) with reduced power consumption includes a power management controller (45) that is operative to select one of a plurality of different power consumption states for a video decoder (10), and, in response to the determination, vary power consumption of at least one operational portion of the video decoder (10). In addition, in one example, a method (200) for reducing power consumption for a video decoder (10) includes determining input stream encoding description data (34) to select one of a plurality of different power consumption states for a video decoder (10) and, in response to the determination, varying power consumption of at least one operational portion of the video decoder (10).Type: ApplicationFiled: August 24, 2010Publication date: December 23, 2010Applicant: ATI Technologies ULCInventors: Greg Sadowski, George Jacobs, Paul Chow
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Patent number: 7804435Abstract: A video decoder (10) with reduced power consumption includes a power management controller (45) that is operative to select one of a plurality of different power consumption states for a video decoder (10), and, in response to the determination, vary power consumption of at least one operational portion of the video decoder (10). In addition, in one example, a method (200) for reducing power consumption for a video decoder (10) includes determining input stream encoding description data (34) to select one of a plurality of different power consumption states for a video decoder (10) and, in response to the determination, varying power consumption of at least one operational portion of the video decoder (10).Type: GrantFiled: August 31, 2006Date of Patent: September 28, 2010Assignee: ATI Technologies ULCInventors: Greg Sadowski, George Jacobs, Paul Chow
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Patent number: 7779177Abstract: A reconfigurable multi-processor computing system including a plurality of configurable processing elements each having a plurality of integrated high-speed serial input/output ports. Interconnects link the plurality of processing elements, wherein at least one of the integrated high-speed serial input/output ports of each processing element is connected by at least one interconnect to at least one of the integrated high-speed serial input/output ports of each other processing element, thereby creating a full mesh network. The full mesh network is located on a processor card, multiples of which may be grouped in a shelf having a backplane card with a shelf controller card for providing cross-connects between processor cards. Multiple shelves may be interconnected to form a large computer system.Type: GrantFiled: August 2, 2005Date of Patent: August 17, 2010Assignee: Arches Computing SystemsInventor: Paul Chow
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Publication number: 20100191791Abstract: A device and method for evaluating multidimensional discrete Fourier transforms (DFT) by eliminating transpose operations by transforming every dimension concurrently. At least one computing node is enabled to evaluate a DFT of one of a multidimensional input data set and a subgroup of the input data set, wherein the subgroup comprises groupings of elements taken from a plurality of selected dimensions of the input data set for subsequent multidimensional DFT operations.Type: ApplicationFiled: January 27, 2010Publication date: July 29, 2010Inventors: Arun Mohanlal Patel, Paul Chow
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Publication number: 20090122870Abstract: The subject matter disclosed herein provides methods and apparatus, including computer program products, for providing intermediate compression or decompression for use with a video decoder and a memory. In one aspect, there is provided a method including receiving information to enable compression of a macroblock. At an intermediate section coupled to a video decoder and a memory, a macroblock may be compressed. The compression of the macroblock may be based on the received information. The compressed macroblock may be provided to memory. Related apparatus, systems, methods, and articles are also described.Type: ApplicationFiled: November 14, 2007Publication date: May 14, 2009Inventors: GREG SADOWSKI, THOMAS E. RYAN, DANIEL WONG, PAUL CHOW
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Publication number: 20080253405Abstract: A method and system for providing error resiliency in processing a multimedia bitstream. The bitstream includes a start code pattern and the method and system detect the start code pattern and track its location to prevent the bitstream processor from overrunning the start code pattern of a subsequent block of multimedia data and corrupting the subsequent block of data. A shift length limiter receives a location of the start code pattern and the location of a current bit pointer. The shift length limiter calculates the number of bits between the start code pattern location and the current bit pointer location. When the shift length limiter receives a bit shift request, the shift length limiter prevents shifting if the number of bits in the bit shift request exceeds the calculated number of bits between the start code pattern location and the current bit pointer location.Type: ApplicationFiled: April 13, 2007Publication date: October 16, 2008Inventors: Patrick Ng, Paul Chow
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Publication number: 20080165860Abstract: Picture order count values are used to calculate a distance scale factor in the H.264 scheme. The distance scale factor can be used as a parameter in temporal direct prediction and weighted prediction. A decoder can operate on video slices containing picture data. Each video slice can contain references to previous and subsequent pictures using POC values. The POC values are stored as a 16-bit difference from an offset. An algorithm utilizes the POC values to output the distance scale factor. Embodiments of the invention can improve the efficiency of a decoder and can reduce storage requirements for POC values associated with H.264 video slices.Type: ApplicationFiled: August 30, 2007Publication date: July 10, 2008Inventors: Zohair Sahraoui, Yingjian He, Paul Chow
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Publication number: 20080092146Abstract: An architecture for a scalable computing machine built using configurable processing elements, such as FPGAs, is provided. The machine can enable implementation of large scale computing applications using a heterogeneous combination of hardware accelerators and embedded microprocessors spread across many FPGAs, all interconnected by a flexible communication network structure.Type: ApplicationFiled: October 9, 2007Publication date: April 17, 2008Inventors: Paul Chow, Christopher Madill, Arun Patel, Manuel Saldana De Fuentes
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Publication number: 20080055119Abstract: A video decoder (10) with reduced power consumption includes a power management controller (45) that is operative to select one of a plurality of different power consumption states for a video decoder (10), and, in response to the determination, vary power consumption of at least one operational portion of the video decoder (10). In addition, in one example, a method (200) for reducing power consumption for a video decoder (10) includes determining input stream encoding description data (34) to select one of a plurality of different power consumption states for a video decoder (10) and, in response to the determination, varying power consumption of at least one operational portion of the video decoder (10).Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Applicant: ATI Technologies Inc.Inventors: Greg Sadowski, George Jacobs, Paul Chow