Abstract: A device and method for evaluating multidimensional discrete Fourier transforms (DFT) by eliminating transpose operations by transforming every dimension concurrently. At least one computing node is enabled to evaluate a DFT of one of a multidimensional input data set and a subgroup of the input data set, wherein the subgroup comprises groupings of elements taken from a plurality of selected dimensions of the input data set for subsequent multidimensional DFT operations.

Abstract: In one aspect, a lateral MOS device is provided. The lateral MOS device includes a gate electrode disposed at least partially in a gate trench to apply a voltage to a channel region, and a drain electrode spaced from the gate electrode, and in electrical communication with a drift region having a boundary with a lower end of the channel region. The device includes a gate dielectric layer in contact with the gate electrode, and disposed between the gate electrode and the drain electrode. The channel region is adjacent to a substantially vertical wall of the gate trench. The device includes a field plate contacting the gate electrode and configured to increase a breakdown voltage of the device.

Abstract: An HEMT type transistor is disclosed that is a normally off type, and in which variations in the gate threshold voltage are small. A transistor is provided with a p-type region, a barrier region, an insulation film, a gate electrode. The channel region is connected to an upper surface of the p-type region. The channel region is n-type or i-type and provided with a first channel region and a second channel region. The barrier region is forming a hetero-junction with an upper surface of the first channel region. The insulation film is connected to an upper surface of the second channel region and an upper surface of the barrier region. The gate electrode faces the second channel region and the barrier region via the insulation film. The first channel region and the second channel region are arranged in series in a current pathway.

Abstract: The subject matter disclosed herein provides methods and apparatus, including computer program products, for providing intermediate compression or decompression for use with a video decoder and a memory. In one aspect, there is provided a method including receiving information to enable compression of a macroblock. At an intermediate section coupled to a video decoder and a memory, a macroblock may be compressed. The compression of the macroblock may be based on the received information. The compressed macroblock may be provided to memory. Related apparatus, systems, methods, and articles are also described.

Abstract: A method and system for providing error resiliency in processing a multimedia bitstream. The bitstream includes a start code pattern and the method and system detect the start code pattern and track its location to prevent the bitstream processor from overrunning the start code pattern of a subsequent block of multimedia data and corrupting the subsequent block of data. A shift length limiter receives a location of the start code pattern and the location of a current bit pointer. The shift length limiter calculates the number of bits between the start code pattern location and the current bit pointer location. When the shift length limiter receives a bit shift request, the shift length limiter prevents shifting if the number of bits in the bit shift request exceeds the calculated number of bits between the start code pattern location and the current bit pointer location.

Abstract: Picture order count values are used to calculate a distance scale factor in the H.264 scheme. The distance scale factor can be used as a parameter in temporal direct prediction and weighted prediction. A decoder can operate on video slices containing picture data. Each video slice can contain references to previous and subsequent pictures using POC values. The POC values are stored as a 16-bit difference from an offset. An algorithm utilizes the POC values to output the distance scale factor. Embodiments of the invention can improve the efficiency of a decoder and can reduce storage requirements for POC values associated with H.264 video slices.

Abstract: An architecture for a scalable computing machine built using configurable processing elements, such as FPGAs, is provided. The machine can enable implementation of large scale computing applications using a heterogeneous combination of hardware accelerators and embedded microprocessors spread across many FPGAs, all interconnected by a flexible communication network structure.

Abstract: In one aspect, there is provided a system including a video decoder and a context manager. The context manager is coupled to the video decoder. The context manager may manage context information for decoding video data (e.g., macroblocks). Specifically, the context manager may prefetch context information representative of a first macroblock before a second macroblock is decoded by the video decoder. The first macroblock may be adjacent to the second macroblock. The prefetched context enables the video decoder to decode the second macroblock.

Abstract: A video decoder (10) with reduced power consumption includes a power management controller (45) that is operative to select one of a plurality of different power consumption states for a video decoder (10), and, in response to the determination, vary power consumption of at least one operational portion of the video decoder (10). In addition, in one example, a method (200) for reducing power consumption for a video decoder (10) includes determining input stream encoding description data (34) to select one of a plurality of different power consumption states for a video decoder (10) and, in response to the determination, varying power consumption of at least one operational portion of the video decoder (10).

Abstract: A semiconductor device includes a graded junction termination extension. A method for fabricating the device includes providing a semiconductor layer having a pn junction, providing a mask layer adjacent to the semiconductor layer, etching the mask layer to form at least two laterally adjacent steps associated with different mask thicknesses and substantially planar step surfaces, and implanting a dopant species through the mask layer into a portion of the semiconductor layer adjacent to the termination of the pn junction. The semiconductor layer is annealed to activate at least a portion of the implanted dopant species to form the graded junction termination extension.

Abstract: A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory. A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients.

Abstract: A reconfigurable multi-processor computing system including a plurality of configurable processing elements each having a plurality of integrated high-speed serial input/output ports. Interconnects link the plurality of processing elements, wherein at least one of the integrated high-speed serial input/output ports of each processing element is connected by at least one interconnect to at least one of the integrated high-speed serial input/output ports of each other processing element, thereby creating a full mesh network. The full mesh network is located on a processor card, multiples of which may be grouped in a shelf having a backplane card with a shelf controller card for providing cross-connects between processor cards. Multiple shelves may be interconnected to form a large computer system.

Abstract: A method and apparatus for compressing image data for storage in a memory device is presented. This is accomplished by separating the image data into a plurality of pixel sets where each pixel set is of a predetermined pixel set size. A discrete cosine transform is then performed on each of the pixel sets to produce a plurality of transform coefficients. These transform coefficients are then compressed to produce a compressed data set. Compressing the transform coefficients preferably includes determining a coefficient set that includes a portion of the transform coefficients that reasonably approximate the pixel set. These coefficients are then mapped to known ranges such that a limited number of bits can encode values throughout these predetermined ranges. The mapped coefficients resulting from the mapping step are then manipulated to fit within a limited number of bits assigned to each coefficient. The limited number of bits is determined partially based on the coefficient set to be compressed.

Abstract: A method and apparatus for decompressing compressed data, which includes video data that has been compressed in accordance with the MPEG 2 standard, wherein the processing begins by retrieving components from a non-local memory at a rate that is independent of the rate in which the components were written into the non-local memory. The components include motion vectors and run/level data. As the components are retrieved from memory, the run/level data is used to produce representations of the uncompressed data. As the representations of the uncompressed data are generated, they are processed based on the motion vector data to recapture the uncompressed data. The uncompressed data is then stored in a frame buffer for subsequent display.

Abstract: Doping of the P type base region in a MOSFET or an IGBT with a combination of boron and one or more of indium, aluminum and gallium, provides a structure having a lower P type doping level in the channel portion of the structure than in the remainder of the structure without requiring counter doping of the channel. The doping level of the emitter region of an MCT is kept high everywhere except in the channel in order to provide a fast turn-off time for the MCT.

Abstract: A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory. A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients.

Abstract: A method and apparatus for decoding a stream of data blocks begins by determining an encoding type of a received data block of the stream of data blocks. When the encoding type of the received data block is of a first encoding type, portions of a reference data block are transferred from non-local memory to a reference section of local memory. As the portions of the reference block are transferred, a first section of local memory is utilized to decode the received data block based on the portions of the reference data block contained in the reference section and a relational data decoding convention. The resulting decoded data block is transferred from the first section of local memory to a second section of local memory.

Abstract: A method and apparatus for video decoding of compressed video data begins by generating a plurality of coefficients based on run level data of two-dimensional frequency components corresponding to the compressed video data. As the coefficients are generated, they are stored in a coefficient section of memory. Once the coefficients have been stored, they are utilized to generate intermediate results. As the intermediate results are being generated, they are stored in an intermediate section of the memory. Next, representations of the video data are generated based on the intermediate results and stored in an output section of the memory. The storing and retrieving of the coefficients, intermediate results, and representations of the video data are done in a time multiplexed manner.

Abstract: A method and apparatus for encoding a stream of data blocks begins when a stream of data blocks is received. The stream of data blocks may include a plurality of sequences of data blocks. The encoding process then continues by storing a first grouping of data blocks of a first sequence in non-local memory. Having stored the first grouping in non-local memory, one of the data blocks is retrieved from the non-local memory. The retrieved data block is then encoded utilizing a working section of local memory based on a relational data encoding convention. Next, the encoding process retrieves a second data block of the first grouping of data blocks from the non-local memory. In addition, portions of the first data block will be retrieved from the non-local memory and provided to a reference section of local memory. The second data block is then encoded in a working section of local memory based on the portions of the first data block and the relational data encoding convention.

Abstract: A method and apparatus for storing and displaying video image data in a video graphics system is accomplished by receiving a video data stream, where the video data stream includes compressed video image data. The video image stream is parsed to separate the compressed video image data from other data within the data stream. The compressed video image data is decompressed to produce video image data that includes a luminosity plane, a first color plane, and a second color plane. Members of the first and second color planes are compacted together to form color pairs where a plurality of the color pairs form a color line. Each of the color lines is interleaved with at least one luminosity line to produce an interleaved plane. The interleaved plane is stored in memory. Portions of the interleaved video image data are retrieved from the interleaved plane. The portions are structured such that video image data that are located near each other within the memory are fetched together.