Abstract: A method and apparatus for sequencing memory accesses in a video graphics system such that page faults are effectively hidden is accomplished by receiving a memory access request from one of a plurality of clients, where the plurality of clients includes both linear clients and tiled memory clients. The clients access data stored in a memory that includes at least two banks. Once the memory request has been received, it is evaluated based on other pending requests in order to determine the optimal ordering pattern for execution of the memory requests. The optimal ordering pattern typically includes sequencing alternating accesses between the two banks of the memory such that when a page fault is occurring in one bank of the memory, a memory access is occurring in the opposing bank. Once the ordering of the memory requests has been performed, the requests are executed.

Abstract: A method and apparatus for video decoding of compressed video data begins by generating a plurality of coefficients based on run level data of two-dimensional frequency components corresponding to the compressed video data. As the coefficients are generated, they are stored in a coefficient section of memory. Once the coefficients have been stored, they are utilized to generate intermediate results. As the intermediate results are being generated, they are stored in an intermediate section of the memory. Next, representations of the video data are generated based on the intermediate results and stored in an output section of the memory. The storing and retrieving of the coefficients, intermediate results, and representations of the video data are done in a time multiplexed manner.

Abstract: A semiconductor device includes a semiconductor substrate having an epitaxial layer surface opposite a drain contact surface; a semiconductor layer adjacent to the epitaxial layer surface of the substrate, the semiconductor layer including material of a first conductivity type; a patterned refractory dielectric layer adjacent to the semiconductor layer; a base region of implanted ions in the semiconductor layer, the base region being of a second conductivity type; a source region of implanted ions in the base region, the source region being of the first conductivity type; a gate insulator layer adjacent to at least a portion of the source and base regions of the semiconductor layer; and a gate electrode over a portion of the gate insulator layer, adjacent to and in physical contact with an outer edge of the patterned refractory dielectric layer, and over at least a portion of the base region between the source region and the patterned refractory dielectric layer.