Patents by Inventor Paul Farrar

Paul Farrar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230320941
    Abstract: The present invention relates to a dental composition and a dental kit comprising a polymerisable adhesive free of a photoinitiator, and a self-cure composite restorative including a redox initiator system. The dental composition cures upon contact between the self-cure composite restorative and the adhesive, to thereby form a dental restoration. The present invention also relates to a method of applying the dental composition, and methods of replacing a dental amalgam with the dental composition, or dental kit, of the present invention.
    Type: Application
    Filed: August 13, 2021
    Publication date: October 12, 2023
    Inventor: Paul FARRAR
  • Publication number: 20220218743
    Abstract: The present invention relates to an aqueous Silver Fluoride (AgF) containing solutions with pH 4.0-5.3.
    Type: Application
    Filed: February 7, 2019
    Publication date: July 14, 2022
    Inventors: Paul FARRAR, Amanda TARGETT, Mingdeng LUO
  • Patent number: 11213462
    Abstract: A dental adhesive composition, having a solvent which is an azeotrope of methyl ethyl ketone with water. Optionally, the azeotropic solvent may comprise in addition, ethanol or isopropanol. The boiling point of the solvent is less than 75° C.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: January 4, 2022
    Assignee: SDI (NORTH AMERICA), INC.
    Inventors: Tony Clayton, Paul Farrar, Manon Agrissais
  • Patent number: 11177104
    Abstract: A device for controlling electron flow is provided. The device comprises a cathode, an elongate electrical conductor embedded in a diamond substrate, an anode, and a control electrode provided on the substrate surface for modifying the electric field in the region of the end of the conductor. A method of manufacturing the device is also provided.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 16, 2021
    Assignee: Evince Technology Limited
    Inventors: Gareth Andrew Taylor, David Andrew James Moran, John Peter Carr, Paul Farrar, Mark Kieran Massey
  • Patent number: 11094496
    Abstract: A device for controlling electron flow is provided. The device comprises a cathode, an elongate electrical conductor embedded in a diamond substrate, an anode, and a control electrode provided on the substrate surface for modifying the electric field in the region of the end of the conductor. A method of manufacturing the device is also provided.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: August 17, 2021
    Assignee: Evince Technology Limited
    Inventors: Gareth Andrew Taylor, David Andrew James Moran, John Peter Carr, Paul Farrar, Mark Kieran Massey
  • Publication number: 20210159039
    Abstract: A device for controlling electron flow is provided. The device comprises a cathode, an elongate electrical conductor embedded in a diamond substrate, an anode, and a control electrode provided on the substrate surface for modifying the electric field in the region of the end of the conductor. A method of manufacturing the device is also provided.
    Type: Application
    Filed: December 3, 2020
    Publication date: May 27, 2021
    Inventors: Gareth Andrew Taylor, David Andrew James Moran, John Peter Carr, Paul Farrar, Mark Kieran Massey
  • Publication number: 20200388460
    Abstract: A device for controlling electron flow is provided. The device comprises a cathode, an elongate electrical conductor embedded in a diamond substrate, an anode, and a control electrode provided on the substrate surface for modifying the electric field in the region of the end of the conductor. A method of manufacturing the device is also provided.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 10, 2020
    Inventors: Gareth Andrew Taylor, David Andrew James Moran, John Peter Carr, Paul Farrar, Mark Kieran Massey
  • Patent number: 9886821
    Abstract: A gaming system and method of rewarding players of electronic gaming machines connected by a network to a host computer which stores player-useable points at a network-accessible location, awards a personal points multiplier to a player, and applies the personal points multiplier to at least some of the points.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: February 6, 2018
    Assignee: IGT
    Inventor: Paul Farrar
  • Publication number: 20170024969
    Abstract: A gaming system and method of rewarding players of electronic gaming machines connected by a network to a host computer which stores player-useable points at a network-accessible location, awards a personal points multiplier to a player, and applies the personal points multiplier to at least some of the points.
    Type: Application
    Filed: October 4, 2016
    Publication date: January 26, 2017
    Inventor: Paul Farrar
  • Patent number: 9466168
    Abstract: A gaming system and method of rewarding players of electronic gaming machines connected by a network to a host computer which stores player-useable points at a network-accessible location, awards a personal points multiplier to a player, and applies the personal points multiplier to at least some of the points.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: October 11, 2016
    Assignee: IGT
    Inventor: Paul Farrar
  • Publication number: 20160063800
    Abstract: A gaming system and method of rewarding players of electronic gaming machines connected by a network to a host computer which stores player-useable points at a network-accessible location, awards a personal points multiplier to a player, and applies the personal points multiplier to at least some of the points.
    Type: Application
    Filed: November 6, 2015
    Publication date: March 3, 2016
    Inventor: Paul Farrar
  • Patent number: 9183701
    Abstract: A gaming system and method of rewarding players of electronic gaming machines connected by a network to a host computer which stores player-useable points at a network-accessible location, awards a personal points multiplier to a player, and applies the personal points multiplier to at least some of the points.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: November 10, 2015
    Assignee: IGT
    Inventor: Paul Farrar
  • Publication number: 20130084994
    Abstract: A gaming system and method of rewarding players of electronic gaming machines connected by a network to a host computer which stores player-useable points at a network-accessible location, awards a personal points multiplier to a player, and applies the personal points multiplier to at least some of the points.
    Type: Application
    Filed: September 4, 2012
    Publication date: April 4, 2013
    Applicant: IGT
    Inventor: Paul Farrar
  • Patent number: 7613031
    Abstract: Circuits, systems, and methods are disclosed for SRAM memories. An SRAM includes memory cells wherein read stability and write stability can be modified by adjusting a well bias signal operably coupled to an N-well of the memory cell. The well bias signal is generated at VDD or at a bias offset from VDD for both the read and the write operations. The memory cells may be adjusted for operation by designing the memory device to be stable relative to local parameter variations with a well bias substantially equal to VDD. The memory cells are then tested for stable read operations and stable write operations. If the write operations are unstable or the read operations are unstable, the well bias is modified and the memory cells are tested again.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: November 3, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Hussein I. Hanafi, Paul Farrar, Leonard Forbes
  • Publication number: 20090073782
    Abstract: Circuits, systems, and methods are disclosed for SRAM memories. An SRAM includes memory cells wherein read stability and write stability can be modified by adjusting a well bias signal operably coupled to an N-well of the memory cell. The well bias signal is generated at VDD or at a bias offset from VDD for both the read and the write operations. The memory cells may be adjusted for operation by designing the memory device to be stable relative to local parameter variations with a well bias substantially equal to VDD. The memory cells are then tested for stable read operations and stable write operations. If the write operations are unstable or the read operations are unstable, the well bias is modified and the memory cells are tested again.
    Type: Application
    Filed: September 17, 2007
    Publication date: March 19, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Hussein I. Hanafi, Paul Farrar, Leonard Forbes
  • Publication number: 20080070392
    Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.
    Type: Application
    Filed: November 1, 2007
    Publication date: March 20, 2008
    Inventors: Paul Farrar, Jerome Eldridge
  • Publication number: 20080057629
    Abstract: A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
    Type: Application
    Filed: October 25, 2007
    Publication date: March 6, 2008
    Inventors: Paul Farrar, Leonard Forbes, Kie Ahn, Joseph Geusic, Arup Bhattacharyya, Alan Reinberg
  • Publication number: 20080048314
    Abstract: A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
    Type: Application
    Filed: October 25, 2007
    Publication date: February 28, 2008
    Inventors: Paul Farrar, Leonard Forbes, Kie Ahn, Joseph Geusic, Arup Bhattacharyya, Alan Reinberg
  • Publication number: 20070164367
    Abstract: Gates of at least one of NMOS transistors and PMOS transistors of a CMOS integrated circuit are formed with a solid-solution alloy of at least two metals. The work function of the gate electrode is tunable by controlling the selection of the metals or the relative proportion of the metals that form a layer of the solid-solution alloy. In one embodiment, a layer of each metal is deposited onto the gate area of a MOS transistor. At least one metal is deposited using atomic layer deposition. The solid-solution alloy is formed by annealing subsequent to the deposition of the metals.
    Type: Application
    Filed: January 18, 2006
    Publication date: July 19, 2007
    Inventors: Leonard Forbes, Paul Farrar, Kie Ahn
  • Patent number: D937496
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: November 30, 2021
    Assignee: Rheon Labs Ltd
    Inventor: Paul Farrar