Abstract: In one embodiment, a resonator device includes a substrate comprising a piezoelectric material and a set of electrodes on the substrate. The electrodes are in parallel and a width of the electrodes is equal to a distance between the electrodes. The RF resonator device further includes a set of switches, with each switch coupled to a respective electrode. The switches are to connect to opposite terminals of an alternating current (AC) signal source and select between the terminals of the AC signal source based on an input signal.

Abstract: Techniques and mechanisms for a transition metal dichalcogenide (TMD) material to be grown on one structure, and then transferred to a different structure. In an embodiment, one or more monolayers of a TMD material are grown on a workpiece comprising a substrate, a growth layer, and a release layer. A material of the substrate is transparent to a wavelength of a laser light, wherein the release layer is opaque to said wavelength. The resulting material stack is then coupled to a target structure, after which a laser ablation is performed to remove some or all of the release layer from between the substrate and the growth layer. The ablation enables the substrate to be separated from the one or more monolayers. In an embodiment, a residue on a surface of the one or more TMD monolayers is an artefact of the layer transfer process.

Abstract: A load transfer device includes a first rotary member and a second rotary member, each of which comprise a plurality of radially projecting petals having a cutout area configured to receive a local portion of an elongated support member. A link body is connected to the first rotary member and the second rotary member. The link body includes a connecting eye configured to attach a load to the load transfer device. A link blocker is connected to the link body. The link blocker has a first blocking member on a first side of the link blocker and a second blocking member on a second side of the link blocker. The first blocking member and the second blocking member are configured to prevent access of lateral portions of the elongated support member to the cutout areas of the radially projecting petals.

Abstract: Methods, systems, and devices for generating personalized health-related predictions from measured physiological data are described. A system may receive, from a wearable device, first physiological data measured from a user via the wearable device through the first time interval. The system may output, via a machine learning model and based on the first physiological data, one or more health related predictions associated with the user during a second time interval. The one or more health-related predictions may include a predicted change in a health related metric during the second time interval based on one or more hypothetical user actions (e.g., expected or anticipated user actions) engaged in by the user between the first time interval and a second time interval. As such, a user interface of a user device associated with the wearable device may display information associated with the one or more health-related predictions prior to the second time interval.

Abstract: A transistor includes a polarization layer above a channel layer including a first III-Nitride (III-N) material, a gate electrode above the polarization layer, a source structure and a drain structure on opposite sides of the gate electrode, where the source structure and a drain structure each include a second III-N material. The transistor further includes a silicide on at least a portion of the source structure or the drain structure. A contact is coupled through the silicide to the source or drain structure.

Abstract: A rail for a rail vehicle track that has a longitudinal extension (L), an apparatus for identifying the rail, and a method for identifying the rail. An identification marker is attached along the longitudinal extension (L) of the rail on an inner side and/or an outer side of the rail. The identification marker is composed of a plurality of symbols, each symbol having at least one partial length (TL) of 0.15 meters, and one identification marker having at least eight symbols. The rail makes it possible for the rail vehicle to identify the rail laid as track during travel in normal operation.

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

Abstract: An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

Abstract: Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.

Abstract: A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed. The compliant layer may be (111) silicon, for example. The SOI substrate may further include another layer that may have one or more of lower electrical resistivity, greater thickness, or a different crystal orientation relative to the compliant substrate layer. A SOI substrate may include a (100) silicon layer advantageous for integrating Group IV devices (e.g., Si FETs), for example. To reduce parasitic coupling between an HFET and a substrate layer of relatively low electrical resistivity, one or more layers of the substrate may be removed within a region below the HFETs. Once removed, the resulting void may be backfilled with another material, or the void may be sealed, for example during back-end-of-line processing.

Abstract: Modern RF front end filters feature acoustic resonators in a film bulk acoustic resonator (FBAR) structure. An acoustic filter is a circuit that includes at least (and typically significantly more) two resonators. The acoustic resonator structure comprises a substrate including sidewalls and a vertical cavity between the sidewalls and two or more resonators deposited in the vertical cavity.

Abstract: Technologies for thermoelectric enhanced cooling on an integrated circuit die are disclosed. In the illustrative embodiment, one or more components are created on a top side of an integrated circuit die, such as a power amplifier, logic circuitry, etc. The one or more components, in use, generate heat that needs to be carried away from the components. A thermoelectric cooler can be created on a back side of the die in order to facilitate removal of heat from the component. In some embodiments, additional structures such as vias filled with high-thermal-conductivity material may be used to further improve the removal of heat from the component.

Abstract: In one embodiment, an integrated circuit includes a silicon substrate, a gallium nitride (GaN) layer above the silicon substrate, a bonding layer above the GaN layer, and a silicon layer above the bonding layer. Further, the integrated circuit includes a first transistor on the GaN layer and a second transistor on the silicon layer.

Abstract: Integrated circuits with III-N metal-insulator-semiconductor field effect transistor (MISFET) structures that employ one or more gate dielectric materials that differ across the MISFETs. Gate dielectric materials may be selected to modulate dielectric breakdown strength and/or threshold voltage between transistors. Threshold voltage may be modulated between two MISFET structures that may be substantially the same but for the gate dielectric. Control of the gate dielectric material may render some MISFETs to be operable in depletion mode while other MISFETs are operable in enhancement mode. Gate dielectric materials may be varied by incorporating multiple dielectric materials in some MISFETs of an IC while other MISFETs of the IC may include only a single dielectric material. Combinations of gate dielectric material layers may be selected to provide a menu of low voltage, high voltage, enhancement and depletion mode MISFETs within an IC.

Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.

Abstract: In one embodiment, an apparatus includes a source region, a drain region, a channel between the source and drain regions, and a polarization layer on the channel. The channel includes gallium and nitrogen, and the polarization layer includes a group III-nitride (III-N) material. The apparatus further includes a gate structure having a first region and a second region. The first region extends into the polarization layer and includes a metal. The second region is coupled to the first region and includes a polycrystalline semiconductor material.

Abstract: In one embodiment, a resonator device includes a substrate comprising a piezoelectric material and a set of electrodes on the substrate. The electrodes are in parallel and a width of the electrodes is equal to a distance between the electrodes. The resonator device further includes a set of switches, with each switch coupled to a respective electrode. The switches are to connect to opposite terminals of an alternating current (AC) signal source and select between the terminals of the AC signal source based on an input signal.

Abstract: An integrated circuit structure comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A polarization layer stack is over the base layer, wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer. A cap layer stack is over the polarization layer to reduce transistor access resistance.

Abstract: A transistor is disclosed. The transistor includes a first part of a gate above a substrate that has a first width and a second part of the gate above the first part of the gate that is centered with respect to the first part of the gate and that has a second width that is greater than the first width. The first part of the gate and the second part of the gate form a single monolithic T-gate structure.