Patents by Inventor Paul Fischer

Paul Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210194459
    Abstract: Techniques are disclosed implementing acoustic wave resonator (AWR) filter architectures to enable integrated solutions requiring significantly less passive components. The primary AWR filter topology leverages the use of parallel resonator branches, each having a relatively narrow bandwidth that may be combined to form an overall broadband filter response. This architecture may be further modified using electronically-controlled switching components to dynamically turn specific branches on or off to tune the filter, thus realizing a programmable broadband solution. Shunt resonators may also be added to the AWR filter topology, which may also be controlled with the use of electronically-controlled switching components to provide further control with respect to roll-off and the location and number of notch frequencies.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Hossein Alavi, Ibrahim Ban, Telesphor Kamgaing, Edris Mohammed, Han Wui Then, Kevin Obrien, Paul Fischer, Johanny Escobar Pelaez, Ved Gund
  • Patent number: 11037817
    Abstract: An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Anup Pancholi, Prashant Majhi, Paul Fischer, Patrick Morrow
  • Publication number: 20210175124
    Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 10, 2021
    Applicant: Intel Corporation
    Inventors: Valluri R. RAO, Patrick MORROW, Rishabh MEHANDRU, Doug INGERLY, Kimin JUN, Kevin O'BRIEN, Paul FISCHER, Szuya S. LIAO, Bruce BLOCK
  • Publication number: 20200411678
    Abstract: A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed. The compliant layer may be (111) silicon, for example. The SOI substrate may further include another layer that may have one or more of lower electrical resistivity, greater thickness, or a different crystal orientation relative to the compliant substrate layer. A SOI substrate may include a (100) silicon layer advantageous for integrating Group IV devices (e.g., Si FETs), for example. To reduce parasitic coupling between an HFET and a substrate layer of relatively low electrical resistivity, one or more layers of the substrate may be removed within a region below the HFETs. Once removed, the resulting void may be backfilled with another material, or the void may be sealed, for example during back-end-of-line processing.
    Type: Application
    Filed: September 28, 2017
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Kevin Lin, Paul Fischer
  • Patent number: 10872820
    Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Bruce Block, Valluri R. Rao, Patrick Morrow, Rishabh Mehandru, Doug Ingerly, Kimin Jun, Kevin O'Brien, Paul Fischer, Szyua S. Liao
  • Publication number: 20200350184
    Abstract: A structure, comprising an island comprising a III-N material. The island extends over a substrate and has a sloped sidewall. A cap comprising a III-N material extends laterally from a top surface and overhangs the sidewall of the island. A device, such as a transistor, light emitting diode, or resonator, may be formed within, or over, the cap.
    Type: Application
    Filed: September 27, 2017
    Publication date: November 5, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul Fischer, Kevin Lin
  • Publication number: 20200312970
    Abstract: Field-effect transistors with buried gates and methods of manufacturing the same are disclosed. An example apparatus includes a source, a drain, and a semiconductor material positioned between the source and the drain. The example apparatus further includes a first gate positioned adjacent the semiconductor material. The example apparatus also includes a second gate positioned adjacent the semiconductor material. A portion of the semiconductor material is positioned between the first and second gates.
    Type: Application
    Filed: December 27, 2017
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Paul Fischer, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 10714446
    Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect with the first active device; a second set of one or more layers; a second active and/or passive device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Anup Pancholi, Prashant Majhi, Paul Fischer, Patrick Morrow
  • Publication number: 20200219772
    Abstract: An integrated circuit structure and methodologies of forming same. In an embodiment, the integrated circuit structure includes a transistor gate structure in a first region of semiconductor material and a diode in a second region of the semiconductor material. The gate structure has a gate electrode of conductive material with a liner along sides and a bottom of the gate electrode. The gate electrode has a gate length less than a threshold dimension value. The diode includes a body of the conductive material in contact with the semiconductor material and includes the liner along sides of the body of conductive material. The body of conductive material has a lateral dimension greater than the threshold dimension value. The liner can include, for example, a gate dielectric and a diffusion barrier in some embodiments. In other embodiments, the liner is the gate dielectric (without any diffusion barrier).
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Applicant: INTEL CORPORATION
    Inventors: RAHUL RAMASWAMY, NIDHI NIDHI, WALID M. HAFEZ, JOHANN C. RODE, PAUL FISCHER, HAN WUI THEN, MARKO RADOSAVLJEVIC, SANSAPTAK DASGUPTA
  • Publication number: 20200211842
    Abstract: An integrated circuit structure comprises a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region include a group III-N semiconductor material, wherein the relaxed buffer stack comprises a plurality of AlGaN material layers and a buffer stack over the plurality of AlGaN material layers, wherein the buffer stack comprises the group III-N semiconductor material and has a thickness of less than approximately 25 nm. A back barrier is in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al. A polarization stack over the relaxed buffer stack.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 2, 2020
    Inventors: Glenn GLASS, Sansaptak DASGUPTA, Han Wui THEN, Marko RADOSAVLJEVIC, Paul FISCHER, Anand MURTHY, Walid HAFEZ
  • Publication number: 20200194551
    Abstract: A device is disclosed. The device includes a polarization layer above a substrate, and a source that includes material that contains As or Sb that extends above the polarization layer. The source and the polarization layer are non-coplanar. The device also includes a drain that includes material that contains As or Sb that extends above the polarization layer. The drain and the polarization layer are non-coplanar. In addition, the device includes a source contact on the source and a drain contact on the drain.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Glenn GLASS, Sansaptak DASGUPTA, Han Wui THEN, Marko RADOSAVLJEVIC, Paul FISCHER, Anand MURTHY
  • Publication number: 20200194578
    Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Rahul RAMASWAMY, Nidhi NIDHI, Walid M. HAFEZ, Johann C. RODE, Paul FISCHER, Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA, Heli Chetanbhai VORA
  • Publication number: 20200194552
    Abstract: An integrated circuit structure comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A polarization layer stack is over the base layer, wherein the polarization layer stack comprises a buffer stack, an interlayer over the buffer stack, a polarization layer over the interlayer. A cap layer stack is over the polarization layer to reduce transistor access resistance.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Sansaptak DASGUPTA, Marko RADOSAVLJEVIC, Han Wui THEN, Nidhi NIDHI, Rahul RAMASWAMY, Johann RODE, Paul FISCHER, Walid HAFEZ
  • Publication number: 20200194575
    Abstract: Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Rahul RAMASWAMY, Nidhi NIDHI, Walid M. HAFEZ, Johann C. RODE, Paul FISCHER, Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA
  • Publication number: 20200194577
    Abstract: An HEMT semiconductor structure is disclosed. The semiconductor structure includes a substrate, a GaN layer above the substrate, a first TDD reducing structure above the substrate and a polarization layer above the GaN layer.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Glenn GLASS, Sansaptak DASGUPTA, Han Wui THEN, Marko RADOSAVLJEVIC, Paul FISCHER, Anand MURTHY, Alexander BADMAEV, Michael S. BEUMER, Sandrine CHARUE-BAKKER
  • Publication number: 20200105744
    Abstract: A device includes a diode that includes a first group III-nitride (III-N) material and a transistor adjacent to the diode, where the transistor includes the first III-N material. The diode includes a second III-N material, a third III-N material between the first III-N material and the second III-N material, a first terminal including a metal in contact with the third III-N material, a second terminal coupled to the first terminal through the first group III-N material. The device further includes a transistor structure, adjacent to the diode structure. The transistor structure includes the first, second, and third III-N materials, a source and drain, a gate electrode and a gate dielectric between the gate electrode and each of the first, second and third III-N materials.
    Type: Application
    Filed: September 29, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul Fischer, Walid Hafez
  • Publication number: 20200105884
    Abstract: A device includes a first Group III-Nitride (III-N) material, a gate electrode above the III-N material, and the gate electrode. The device further includes a tiered field plate, suitable for increasing gate breakdown voltage with minimal parasitics. In the tiered structure, a first plate is on the gate electrode, the first plate having a second sidewall laterally beyond a sidewall of the gate, and above the III-N material by a first distance. A second plate on the first plate has a third sidewall laterally beyond the second sidewall and above the III-N material by a second distance, greater than the first. A source structure and a drain structure are on opposite sides of the gate electrode, where the source and drain structures each include a second III-N material.
    Type: Application
    Filed: September 29, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Walid Hafez, Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Paul Fischer
  • Publication number: 20200105880
    Abstract: A transistor includes a polarization layer above a channel layer including a first III-Nitride (III-N) material, a gate electrode above the polarization layer, a source structure and a drain structure on opposite sides of the gate electrode, where the source structure and a drain structure each include a second III-N material. The transistor further includes a silicide on at least a portion of the source structure or the drain structure. A contact is coupled through the silicide to the source or drain structure.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul Fischer, Walid Hafez
  • Publication number: 20200105882
    Abstract: Transistor structures for logic, power management, or radio frequency integrated circuits, devices and computing platforms employing such transistor structures, and methods for forming them are discussed. The transistor structures include a fin structure having multiple graded III-N material layers with polarization layers therebetween. The fin structure provides a multi-gate multi-nanowire confined transistor architecture for improved performance.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA, Paul FISCHER, Walid HAFEZ
  • Publication number: 20200098885
    Abstract: A transistor comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A gate stack is above the channel region, the gate stack comprises a gate electrode and a composite gate dielectric stack, wherein the composite gate dielectric stack comprises a first large bandgap oxide layer, a low bandgap oxide layer, and a second large bandgap oxide layer to provide a programmable voltage threshold. Source and drain regions are adjacent to the channel region.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DUSGUPTA, Paul FISCHER, Walid HAFEZ