Patents by Inventor Paul Frank

Paul Frank has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250043345
    Abstract: This invention provides analytical devices for use in various applications, including detection of single-molecule analytical reactions. Methods for propagating optical energy within a substrate are provided. Devices comprising waveguide substrates, dielectric omnidirectional reflectors, and optical couplers are provided. Waveguide substrates with improved uniformity of optical energy intensity across one or more waveguides and enhanced waveguide illumination efficiency within an analytic detection region of the arrays are provided.
    Type: Application
    Filed: July 16, 2024
    Publication date: February 6, 2025
    Inventors: Cheng Frank Zhong, Paul Lundquist, Mathieu Foquet, Jonas Korlach, Hovig Bayandorian
  • Patent number: 12215341
    Abstract: There are provided herein, inter alia, complexes, compositions and methods for the delivery of nucleic acid into a cell in vivo. The complexes, compositions and methods may facilitate complexation, protection, delivery and release of oligonucleotides and polyanionic cargos into target cells, tissues, and organs both in vitro and in vivo.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: February 4, 2025
    Assignee: THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY
    Inventors: Tim R. Blake, Robert M. Waymouth, Paul Wender, Ronald Levy, Ole Audun Werner Haabeth, Matthew Frank, Adrienne Sallets
  • Patent number: 12202794
    Abstract: A method for isomerizing alpha olefins to produce an isomerization mixture comprising branched olefins can comprise contacting an olefinic feed including one or more C10-C20 alpha olefins with a catalyst under skeletal isomerization conditions, wherein the catalyst comprises a molecular sieve having an MRE topology; and obtaining an isomerization mixture comprising one or more C10-C20 branched olefins.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: January 21, 2025
    Assignee: ExxonMobil Chemical Patents Inc.
    Inventors: Sina Sartipi, Wenyih Frank Lai, Roxana Perez Velez, Renyuan Yu, Paul F. Keusenkothen, Zsigmond Varga
  • Patent number: 12205870
    Abstract: A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.
    Type: Grant
    Filed: May 16, 2023
    Date of Patent: January 21, 2025
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
  • Patent number: 12159854
    Abstract: A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.
    Type: Grant
    Filed: December 27, 2023
    Date of Patent: December 3, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Paul Frank, Thomas Heinelt, Oliver Schilling, Sven Schmidbauer, Frank Wagner
  • Publication number: 20240387899
    Abstract: A cooling device for an energy storage, which has multiple cooling channels through which a coolant can flow and an adjusting device which includes at least one temperature-dependently adjustable adjusting element, through the adjustment of which a flow characteristic of at least one of the cooling channels can be changed. The cooling device is designed as an inter-cell cooling element for arrangement in an intermediate space between a first and a second storage cell of the energy storage. Through the displacement of the at least one adjusting element the flow characteristic of at least one first of the cooling channels can be changed with respect to a second of the cooling channels.
    Type: Application
    Filed: May 1, 2024
    Publication date: November 21, 2024
    Applicant: AUDI AG
    Inventors: Paul FRANK, Carsten LORENZ, Eduard MAIN
  • Publication number: 20240202774
    Abstract: An apparatus is provided for determining an output based on a membership of the user in an audience. The apparatus includes a processor for determining a threshold associated with membership of an audience, determining a score relating to a user in dependence on one or more activities of the user associated with the audience wherein at least one activity is determined based on contextual information of the user, and determining the membership of the user in the audience in dependence on whether the score exceeds the threshold. Also included is a user interface and/or a communication interface for providing an output for the user based on the membership of the user in the audience.
    Type: Application
    Filed: April 12, 2022
    Publication date: June 20, 2024
    Inventors: Abhishek Sen, Christopher John Watts, Hector Durham, Eoin Robert Groat, Vincent Paul Frank Groff
  • Publication number: 20240128226
    Abstract: A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Paul Frank, Thomas Heinelt, Oliver Schilling, Sven Schmidbauer, Frank Wagner
  • Publication number: 20240096842
    Abstract: A method for fabricating a SiC power semiconductor device includes: providing a SiC power semiconductor die; depositing a metallization layer over the power semiconductor die, the metallization layer including a first metal; arranging the power semiconductor die over a die carrier such that the metallization layer faces the die carrier, the die carrier being at least partially covered by a plating that includes Ni; and diffusion soldering the power semiconductor die to the die carrier such that a first intermetallic compound is formed between the power semiconductor die and the plating, the first intermetallic compound including Ni3Sn4.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Ralf Otremba, Gregor Langer, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
  • Publication number: 20240035289
    Abstract: A lighting system has an elongate bracket having a recess for receiving an edge of a wall member in use such that the bracket extends along the edge of the wall member; a groove extending along the length of the bracket and spaced from the rear wall by an intermediate wall portion; and an electroluminescent wire extending along the length of the bracket at a position within the groove in front of the rear wall such that the electroluminescent wire is exposed in use.
    Type: Application
    Filed: January 28, 2022
    Publication date: February 1, 2024
    Inventors: Kevin Tattersall, Christopher Paul Frank Shepard
  • Patent number: 11887961
    Abstract: A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: January 30, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Paul Frank, Thomas Heinelt, Oliver Schilling, Sven Schmidbauer, Frank Wagner
  • Publication number: 20240030502
    Abstract: In an embodiment, a semiconductor device is provided that includes a semiconductor die having a front side, a rear side opposing the front side, and side faces, a first transistor device having a first source pad and a first gate pad on the front side, and a second transistor device having a second source pad and a second gate pad on the front side. The first and second transistor devices each have a drain that is electrically coupled to a common drain pad on the rear side of the semiconductor die. The drain pad has an upper surface and side faces and at least a central portion of the upper surface is covered by a first electrically insulating layer.
    Type: Application
    Filed: June 9, 2023
    Publication date: January 25, 2024
    Inventors: Christian Ranacher, Evelyn Napetschnig, Sandra Ebner, Mark Pavier, Stanislav Vitanov, Paul Frank
  • Publication number: 20230364037
    Abstract: The present invention provides novel drug combinations, pharmaceutical compositions, as well as methods involving novel therapeutic regimes for targeting cancer stem cells, as well as methods of use thereof, for the treatment and management of cancerous and non-cancerous tumours in a patient. In particular, the present invention provides novel drug combinations and pharmaceutical compositions that target components of the Renin Angiotensin System shown to expressed by cancer stem cells.
    Type: Application
    Filed: May 22, 2023
    Publication date: November 16, 2023
    Inventors: Paul Frank Davis, Tinte Itinteang, Reginald Walter Marsh, Swee Thong Tan
  • Publication number: 20230290709
    Abstract: A semiconductor package includes a power semi conductor chip comprising SiC, a leadframe part including Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint includes at least one intermetallic phase.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 14, 2023
    Inventors: Ralf Otremba, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
  • Patent number: 11688670
    Abstract: A semiconductor package includes a power semiconductor chip comprising SiC, a leadframe part comprising Cu, wherein the power semiconductor chip is arranged on the leadframe part, and a solder joint electrically and mechanically coupling the power semiconductor chip to the leadframe part, wherein the solder joint comprises at least one intermetallic phase.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 27, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Paul Frank, Alexander Heinrich, Alexandra Ludsteck-Pechloff, Daniel Pedone
  • Publication number: 20230167606
    Abstract: A fibrous structure may have a lower side and an upper side, and may comprise three-dimensional, out-of-plane features formed by knuckles on a papermaking belt, the features may exhibit at least two Z-direction spatially separated surfaces defined in order spatially with respect to the lower side, wherein each successive surface progressing in a Z-direction away from the lower side may have a projected area less than the projected area of the surface adjacent and closer to the lower side, and each projected area may be bounded completely by the area of the projected area of the surface adjacent and closer to the lower side.
    Type: Application
    Filed: January 25, 2023
    Publication date: June 1, 2023
    Inventors: Geoffrey Eugene Seger, John Allen Manifold, Osman Polat, Andrew Paul Frank Milton, Robert Scadding Moir, Daniel Graham Ward, Richard Bown
  • Patent number: 11629462
    Abstract: A textured mask comprising a film. The film can have a first substantially continuously flat surface lying in a first plane and a second surface opposite the first surface lying in a second plane substantially parallel to the first plane. The second surface is interrupted by a plurality of cavities, each of the cavities having a first depth defined by a third surface lying in a third plane substantially parallel to the first and second planes. The depth of the cavities can be at a distance of from about 0.1 mm to about 5 mm from the second plane. The textured mask is at least partially coated with an opaque masking agent. The textured mask can make a correspondingly structured three-dimensional papermaking belt, which can make correspondingly structured three-dimensional fibrous structure.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: April 18, 2023
    Assignee: The Procter & Gamble Company
    Inventors: Geoffrey Eugene Seger, John Allen Manifold, Osman Polat, Andrew Paul Frank Milton, Robert Scadding Moir, Daniel Graham Ward, Richard Bown
  • Patent number: 11615963
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: March 28, 2023
    Assignee: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Publication number: 20230090708
    Abstract: The present invention relates to methods and compositions for the treatment of hemangioma, and particularly, but not exclusively, methods and compositions for the treatment of infantile hemangioma. In certain aspects, the methods comprise locally administering an ACE inhibitor or an ATIIR2 antagonist to a subject. In other aspects, the methods comprise systemically administering two or more of an ACE inhibitor, a beta-blocker and an ATIIR2 antagonist. The present invention also relates to compositions that are suitable for local administration and comprise: an ACEi and a beta-blocker; an ACEi and an ATIIR2 antagonist; a beta-blocker and an AT11R2 antagonist; or, an ACEi, a beta-blocker, and an AT11R2 antagonist.
    Type: Application
    Filed: January 29, 2021
    Publication date: March 23, 2023
    Inventors: Paul Frank DAVIS, Sean Marshall MACKAY, Erin Fay PATERSON, Swee Thong TAN, Eng Wui TAN
  • Publication number: 20230063856
    Abstract: A semiconductor device includes a semiconductor die including a first side and an opposing second side, a first metallization layer arranged on the first side, a Ni including layer arranged on the second side, wherein the Ni including layer further includes one or more of Si, Cr and Ti, and a SnSb layer arranged on the Ni comprising layer, wherein an amount of Sb in the SnSb layer is in the range of 2 wt % to 30 wt %.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 2, 2023
    Inventors: Oliver Schilling, Roman Immel, Joachim Seifert, Altan Toprak, Frank Wagner, Ulrich Wilke, Lars Boewer, Paul Frank