Patents by Inventor Paul Ho

Paul Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260110283
    Abstract: An automobile air intake system that has a detachable airbox cover for accessing an air filter and a transparent window assembly for visually inspecting the air filter is contemplated. A user may inspect the air filter by viewing the air filter through the transparent window assembly. The user may directly access and replace an air filter by removing an airbox cover. The window assembly, airbox cover, and the airbox are releasably secured to each other with magnets and magnetic materials. The airbox has an internal velocity stack for improving engine performance.
    Type: Application
    Filed: September 18, 2025
    Publication date: April 23, 2026
    Applicant: Injen Technology Company, Ltd.
    Inventors: Ron Delgado, Paul Ho
  • Patent number: 7452808
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: November 18, 2008
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Publication number: 20060268756
    Abstract: Embodiments of systems and methods for efficient hand-off in a wireless network employ a neighbor report which may include, in addition to more convention information about neighboring access point, search thresholds, target beacon transmission time of neighboring access points, and execution thresholds. The present systems and methods also provide a mechanism of updating neighbor report and its elements. A faster and lower spectrum cost active search scheme based on sending a null packet may also be used by the systems and methods.
    Type: Application
    Filed: May 3, 2005
    Publication date: November 30, 2006
    Applicant: Hong Kong Applied Science and Technology Research Institute Co., Ltd.
    Inventors: Yan Wang, Cheong Wong, Jingyi He, Piu Wong, J.D. Qu, Soung Liew, Vincent Lau, Paul Ho, Gary Jiang
  • Patent number: 7060613
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: June 13, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Xu Yi
  • Patent number: 6967162
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: November 22, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Publication number: 20050224921
    Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit.
    Type: Application
    Filed: June 9, 2005
    Publication date: October 13, 2005
    Inventors: Subhash Gupta, Paul Ho, Sangki Hong
  • Publication number: 20050205522
    Abstract: A polishing method is achieved comprising the following steps. A layer made of material containing a metal as a main component over a substrate having recessed portions on a surface thereof so as to fill the recessed portions with the metal layer is formed. The metal is Cu, a Cu alloy, Al, or an Al alloy. The metal layer is polished by a chemical mechanical polishing method using a slurry including a polishing agent. The polishing agent contains a chemical agent and an etching agent. The chemical agent includes at least a carbonyl derivative of benzotriazole and is responsible for forming a protective film on the surface of the metal layer by reacting with the material containing a metal as a main component. The etching agent is responsible for etching the material containing a metal as a main component.
    Type: Application
    Filed: May 16, 2005
    Publication date: September 22, 2005
    Inventors: Paul Ho, Mei Zhou, Chockalingam Ramasamy
  • Publication number: 20050112799
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 26, 2005
    Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho, Yi Xu
  • Publication number: 20050093163
    Abstract: Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.
    Type: Application
    Filed: December 13, 2004
    Publication date: May 5, 2005
    Inventors: Paul Ho, Ki-Don Lee, Ennis Ogawa, Hideki Matsuhashi
  • Publication number: 20050090039
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: November 15, 2004
    Publication date: April 28, 2005
    Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Publication number: 20050090102
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Application
    Filed: November 15, 2004
    Publication date: April 28, 2005
    Inventors: Simon Chooi, Yakub Aliyu, Mei Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Patent number: 6565664
    Abstract: An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: May 20, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Subhash Gupta, Simon Chooi, Paul Ho, Mei Sheng Zhou
  • Publication number: 20020115580
    Abstract: An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.
    Type: Application
    Filed: April 24, 2002
    Publication date: August 22, 2002
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Subhash Gupta, Simon Chooi, Paul Ho, Mei Sheng Zhou
  • Patent number: 6394114
    Abstract: An inexpensive and safe copper removal method in the fabrication of integrated circuits is described. Copper is stripped or removed by a chemical mixture comprising an ammonium salt, an amine, and water. The rate of copper stripping can be controlled by varying the concentration of the ammonium salt component and the amount of water in the mixture. Also a novel chemical mixture for stripping copper and removing copper contamination is provided. The novel chemical mixture for removing or stripping copper comprises an ammonium salt, an amine, and water. For example, the novel chemical mixture may comprise ammonium fluoride, water, and ethylenediamine in a ratio of 1:1:1.
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: May 28, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Subhash Gupta, Simon Chooi, Paul Ho, Mei Sheng Zhou
  • Patent number: 6391783
    Abstract: A method of forming a metal plug, comprising the following steps. An etched dielectric layer, over a conductive layer, over a semiconductor structure are provided. The etched dielectric layer having a via hole and an exposed periphery. The etched dielectric layer is treated with at least one alkaline earth element source to form an in-situ metal barrier layer within the dielectric layer exposed periphery. A metal plug is formed within the via hole wherein the in-situ metal barrier layer prevents diffusion of the metal from the metal plug into the dielectric oxide layer.
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: May 21, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: John Sudijono, Yakub Aliyu, Mei Sheng Zhou, Simon Chooi, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Patent number: 6365508
    Abstract: A new method to avoid post-etch cleaning in a metallization process is described. An insulating layer is formed over a first metal line in a dielectric layer overlying a semiconductor substrate. A via opening is etched through the insulating layer to the first metal line whereby a polymer forms on sidewalls of the via opening. The polymer is treated with a fluorinating agent whereby the polymer is converted to an inert layer. Thereafter, a second metal line is formed within the via opening wherein the inert layer acts is as a barrier layer to complete the metallization process in the fabrication of an integrated circuit device.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: April 2, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Xu Yi, Simon Chooi, Yakub Aliyu
  • Patent number: 6350689
    Abstract: A method of removing copper contamination from a semiconductor wafer, comprising the following steps. A semiconductor wafer having copper contamination thereon is provided. An oxidizing radical containing downstream plasma is provided from a first source (alternatively halogen (F2, Cl2, or Br2) may be used as on oxidizing agent). A vaporized chelating agent is provided from a second source. The oxidizing radical containing downstream plasma and vaporized chelating agent are mixed to form an oxidizing radical containing downstream plasma/vaporized chelating agent mixture. The mixture is directed to the copper contamination so that the mixture reacts with the copper contamination to form a volatile product. The volatile product is removed from the proximity of the wafer.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: February 26, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Paul Ho, Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Yi Xu
  • Patent number: 6340608
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal track thereover are provided. A metal bump is formed over the exposed metal terminating pad. A photosensitive resin plug is formed over the metal bump. The metal bump of the semiconductor chip is aligned with the corresponding metal track on the separate substrate. The photosensitive resin plug over the metal bump is mated with the corresponding the metal track. The photosensitive resin plug is exposed to UV light to cure the photosensitive resin plug, permanently attaching the metal bump of the semiconductor chip to the corresponding metal track of the separate substrate.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: January 22, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho, Xu Yi
  • Patent number: 6309982
    Abstract: A method for reducing copper diffusion into an inorganic dielectric layer adjacent to a copper structure by doping the inorganic dielectric layer with a reducing agent (e.g. phosphorous, sulfur, or both) during plasma enhanced chemical vapor deposition. The resulting doped inorganic dielectric layer can reduce copper diffusion without a barrier layer reducing fabrication cost and cycle time, as well as reducing RC delay.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: October 30, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yi Xu, Yakub Aliyu, Mei-Sheng Zhou, John Leonard Sudijono, Subhash Gupta, Sudipto Ranendra Roy, Paul Ho
  • Patent number: 6255266
    Abstract: A method of cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware without corroding or damaging the equipment parts and surfaces in the event of wafer breakage and non-wafer breakage is described. A solution comprising an alkyldione peroxide, a stabilizing agent, and alcohols is used to oxidize the metal and form soluble complexes which are removed by the cleaning solution. Also, a novel alkyldione peroxide solution for cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware in the event of wafer breakage and non-wafer breakage is provided.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: July 3, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Subhash Gupta, Simon Choo I, Mei Sheng Zhou, Paul Ho