Architectures for an Implantable Medical Device System
An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicate with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG without the need for a major redesign of the main IPG IC.
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This is a continuation of U.S. patent application Ser. No. 11/767,636, filed Jun. 25, 2007, to which priority is claimed and which is incorporated herein by reference in its entirety.
FIELD OF THE INVENTIONThe present invention relates generally to implantable medical devices, and more particularly, to improved architectures for the circuitry in an implantable medical device.
BACKGROUNDImplantable stimulation devices are devices that generate and deliver electrical stimuli to body nerves and tissues for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, retinal stimulators to treat blindness, muscle stimulators to produce coordinated limb movement, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other neural stimulators to treat urinary incontinence, sleep apnea, shoulder sublaxation, etc. The present invention may find applicability in all such applications, although the description that follows will generally focus on the use of the invention within a Spinal Cord Stimulation (SCS) system, such as that disclosed in U.S. Pat. No. 6,516,227 (“the '227 patent”), which is incorporated herein by reference in its entirety.
Spinal cord stimulation is a well-accepted clinical method for reducing pain in certain populations of patients. As shown in
As shown in
Further details concerning the structure and function of typical IPGs and IPG systems are disclosed in U.S. patent application Ser. No. 11/305,898, filed Dec. 14, 2005, which is incorporated herein by reference.
A traditional architecture 50 for the circuitry inside of an IPG 100 is shown in
Circuitry involved in providing a predictable therapy of stimulation is provided by a digital integrated circuit (IC) 70 and an analog IC 80. In one application, the digital IC 70 contains stimulation control logic, such as the various timers that are used by the IPG's timing channels to provide a stimulation pulse train with a particular timing. The analog IC 80 receives data from the digital IC 70 via a serial link, where such data is converted to analog signals by a digital-to-analog converter (DAC) 82, which in turn ultimately provides the stimulus to the electrodes (E1 . . . EN). Additionally, an analog-to-digital (A/D) converter 74 is used to inform the microcontroller 60 of various analog voltages being produced or monitored on the analog IC 80, such as various reference voltages, the stimulation compliance voltage, etc., and within the charging 64 and telemetry 62 blocks. Although shown as integrated with the microcontroller 60, the A/D converter 74 could also be a discrete component outside of the microcontroller 60.
In one embodiment, the microcontroller 60, the digital IC 70, and the analog IC 80 comprise discrete ICs each comprising one of the components 20 on the IPG's printed circuit board 16 (see
Having briefly described the functional blocks in architecture 50, it should be noted that it is not important to the present disclosure to understand the detailed workings of those blocks. (The reader can consult the above-incorporated '898 application should a greater knowledge of each of the functional blocks be desired). Instead, what is important to understand is the manner in which the functional blocks are interconnected. As one skilled in the art will understand, central to the operation of architecture 50 is the microcontroller 60, which ultimately receives and issues all commands from and to the other blocks. Furthermore, it can be noticed that the various interconnections between the blocks vary in type and complexity, with some connections being serial in nature, and others comprising single data lines or comprising data digital busses. Moreover, some of the blocks lack direct connections with other blocks, and hence must communicate through intermediary blocks. For example, the microcontroller 60 must, at least in part, communicate with the analog IC 80 through the digital IC 70.
Such inter-connectivity adds to the expense of the IPG 100 and its complexity. Moreover, it also makes it difficult to adapt a particular architecture to desired changes and/or newer IPG revisions. For example, the changing of one of the functional blocks may require significant corresponding changes in other functional blocks, making upgrades or revisions expensive.
Additionally, space within an IPG 100 is limited, because IPGs are preferably as small as possible to make the implant as unobtrusive as possible for the patient. In this regard, the architecture 50 of
This disclosure presents a solution to this problem in the art of implantable medical devices via an improved IPG architecture.
An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a single integrated circuit (IC). Each of the functional blocks communicate with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG without the need for a major redesign of the main IPG IC.
In a preferred embodiment, each of the illustrated functional blocks are integrated within a single integrated circuit (IC) 200. Because the IPG IC 200 as illustrated contains both analog and digital signals, the IC 200 would comprise a mixed mode chip. However, it is not strictly necessary that the architecture 150 be realized on a single IC 200 as shown. Moreover, it should be understood that certain other circuitry components within the IPG 100 (such as the data and charging coils 96 and 18, the power source 26, and external memory 66, etc.) would logically reside outside of the IC 200. That being said, it is still preferred that as many as possible of the functional blocks within the IPG be consolidated on the IC 200, as this increases yield, increases reliability, decreases space of the electronic circuitry within the IPG, decreases power consumption of the circuitry within the IPG 100, etc.
Each of the various functional blocks in the improved IPG architecture 150 communicate with the centralized bus 190 via bus interface circuitry 215, which will be discussed in further detail later. Preferably, all other non-bus-based communications between the functional blocks are kept to a minimum, but some such communications are beneficial. For example, as shown, various interrupts (INT1, INT2, . . . ) communicate directly with an interrupt controller 173, which allows their issuance to be immediately recognized without the potential delays involved in protocol-based communication through the centralized bus 190. For example, INT2 can inform the interrupt controller 173 if the power source 26 is charged to a dangerous level, so that operation of the IC 200 might be temporarily curtailed if necessary. In another off-bus communication, an analog bus 192 is used to send various analog signals to a A/D block 74 where such voltages can be digitized and made available to other functional blocks via the centralized bus 190 as needed.
While it is not terribly important to the disclosed improved IPG architecture 150 to understand the operation of each of the functional blocks, note from
In another important difference with the architecture 50 of the prior art (
As can be seen in
The various signals comprising the bus 190 can be seen in
As one skilled in the art will appreciate, communications in an IPG system such as one including the IC 200 of
As shown, the protocol uses a fairly simple address-before-data scheme in which an address is followed by pertinent data for that address, etc. To help discern between address and data, the address latch enable signal (ALE) is active only upon the issuance of an address, which allows the address to be latched upon the rising edge of the clock. Whether the data corresponding to a particular address is to be written or read depends on the assertion of the write and read enable signals (*W/E; *R/E). Of course, this protocol is merely exemplary and other protocols and formats could be use for communication on the centralized bus 190.
The nature of the protocol of
To assist the various functional blocks in recognizing pertinent addresses, and to ensure each block's ability to function in accordance with the centralized bus 190's protocol, each block contains bus interface circuitry 215, which is shown in
With the bus interface circuitry 215 allowing each functional block to communicate using the protocol established for the bus 190, it now becomes a relatively simple endeavor to make changes to the various functional blocks to fix circuit errors, and/or to upgrade the IC 200 for use in next-generation IPGs. This is because each of the blocks' circuitry can be changed without worries that such changes will necessitate other changes in related blocks, or otherwise perturb the operation of other blocks. Functional blocks can be independently designed and verified in parallel, saving time and hassle during the design process.
Another advantage of the improved architecture 150 is the ability to easily modify or add functionality to the IPG 100 outside of the IC 200. For example, future improvements may require the IPG to store more data than is otherwise available in the on-chip memory 177 or the off-chip memory 66 (see
In another example showing how the disclosed architecture 150 benefits system integration, the capacity of the system can be effectively doubled by the addition of another IC 200′ similarly constructed to the first IC 200. This would allow the IPG 100 in which the IC 200 and 200′ were placed to provide 32 stimulation electrodes, i.e., 16 each from both of the ICs. In other words, the capacity of the IPG can be increased by simply “daisy chaining” a plurality of stimulation ICs together. In such an embodiment, it may be beneficial that the internal controller 160 in one of the ICs 200 or 200′ be inactivated so only one controller 160 acts as the master controller for the system. Alternatively, the IPG system can utilize both controllers 160 in both of the ICs 200 and 200′, although this requires arbitration between the two controllers to prevent potential conflicts, a subject discussed below with reference to
Other devices may also be added external to the IC 200 via the bus 190. For example, one particularly interesting application enabled by the use of architecture 150 is the ability to place at least some degree of systemic control outside of the IC 200. For example, in
However, to add additional control via an external microcontroller 240, additional communications may be required between the internal controller 160 and the external microcontroller 240 to ensure no conflict between the two control mechanisms.
In recognition of the possibility of external control, the internal controller 160 is provided with additional functionality as illustrated in
In other implementations, the controller select bit can comprise data sent via the bus 190 using the bus 190's protocol. In such an implementation, the CSB data could be viewed as a control “token” which is passed between the internal controller 160 and the external microcontroller 240 via the bus 190. Such a purely bus-based method for arbitration between the controllers is easily implemented. However, because it is easier to illustrate the passage of control between the two controllers 160 and 240 using a discrete non-bus based signal approach, that approach is illustrated below and in the figures.
As shown, the internal controller 160 is designed with two registers, a command register 220 and a command owner register 230, shown in detail in
The use of command register 220 and command owner register 230 to issue a controller select bit (CSB) 245 is illustrated in
This process is explained in detail with respect to
With the CSB 245 issued, it is now known which of the controllers 160 or 240 is to execute the command in question, and thus various actions are taken accordingly. If CSB=‘0 ’, denoting the internal controller 160, little needs to be accomplished but for that controller 160 to execute the command. As a default, to ensure that the external microcontroller 240 will not conflict with execution of the command by the internal controller 160, arbitration logic 246 programmed into the external controller 240 disables the external controller's bus drivers 242 upon sensing that CSB=0. In contrast, the internal controller bus drivers 212 are enabled by the stored controller enable register bit 250 (an active low signal). After the internal controller 160 has executed its command, the system waits for the next command, and the method repeats, etc.
However, if CSB=‘1’, denoting the external microcontroller 240, extra steps are taken to allow control to be temporarily shifted to the external microcontroller 240. Specifically, the arbitration logic 246 in the external controller recognizes upon sensing that CSB=‘1’ that it is in control, and enables its bus drivers 242. By contrast, the internal controller bus drivers 212 are disabled. Additionally, upon recognizing that CSB=‘1’, the arbitration logic 246 retrieves the command (i.e., its command) as stored in the command register 220 by requesting a read via the bus 190 from that register's address (ADDR[CMD]). Once received, the external controller 240 executes the command.
With the command executed by the external microcontroller 240, the remaining steps illustrated in
The flow of
Although particular embodiments of the present invention have been shown and described, it should be understood that the above discussion is not intended to limit the present invention to these embodiments. It will be obvious to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. Thus, the present invention is intended to cover alternatives, modifications, and equivalents that may fall within the spirit and scope of the present invention as defined by the claims.
Claims
1. An implantable stimulator device comprising a plurality of first electrodes and a plurality of second electrodes configured to provide stimulation to a patient's tissue, comprising:
- a first integrated circuit comprising a first stimulation circuitry block for controlling stimulation of the plurality of first electrodes;
- a second integrated circuit comprising a second stimulation circuitry block for controlling stimulation of the plurality of first electrodes; and
- a bus in communication with both the first and second integrated circuits, wherein communications on the bus occurs in accordance with a bus protocol.
2. The device of claim 1, wherein the first and second stimulation circuitry blocks respectively comprise first and second digital-to-analog converter circuitry for respectively providing stimulation to the plurality of first and second electrodes.
3. The device of claim 1, further comprising an electrode array coupled to the first and second electrodes.
4. The device of claim 3, wherein the electrode array comprises a plurality of electrode leads.
5. The device of claim 1, further comprising a controller in communication with the bus, wherein the controller controls the first and second integrated circuits via the bus.
6. The device of claim 5, wherein the controller comprises an integrated circuit separate from the first and second integrated circuits.
7. The device of claim 5, wherein the controller resides on one of the first or second integrated circuits.
8. The device of claim 1, wherein the first and second integrated circuits are similarly constructed.
9. The device of claim 1, wherein the protocol comprises an address-before-data protocol.
10. The device of claim 9, wherein the bus comprises a plurality of signals for carrying in parallel both data and addresses, wherein the data and addresses are time-multiplexed on the plurality of signals.
11. The device of claim 10, wherein the bus comprises a write enable signal line and a read enable signal line.
12. The device of claim 11, wherein the bus comprises an address latch enable signal line for latching a read or write address.
13. The device of claim 1, wherein each of the first and second integrated circuits further comprises a plurality of functional blocks each coupled to the bus.
14. The device of claim 1, wherein the first and second stimulation circuitry blocks and the plurality of functional blocks on the first and second integrated circuits each couple to the bus using bus interface circuitry.
15. The device of claim 1, wherein the first integrated circuit comprises a master for controlling the second integrated circuit as a slave.
16. An implantable stimulator device comprising a plurality of first electrodes and a plurality of second electrodes configured to provide stimulation to a patient's tissue, comprising:
- a first integrated circuit comprising a first stimulation circuitry block for controlling stimulation of the plurality of first electrodes;
- a second integrated circuit comprising a second stimulation circuitry block for controlling stimulation of the plurality of first electrodes, wherein the first and second integrated circuits are similarly constructed; and
- a controller for controlling the first and second integrated circuits.
17. The device of claim 16, wherein the first and second stimulation circuitry blocks respectively comprise first and second digital-to-analog converter circuitry for respectively providing stimulation to the plurality of first and second electrodes.
18. The device of claim 16, further comprising an electrode array coupled to the first and second electrodes.
19. The device of claim 18, wherein the electrode array comprises a plurality of electrode leads.
20. The device of claim 16, wherein the controller comprises an integrated circuit separate from the first and second integrated circuits.
21. The device of claim 16, wherein the controller resides on one of the first or second integrated circuits.
22. The device of claim 16, wherein the first and second integrated circuits and the controller are each coupled to a communication bus, wherein communication on the bus occurs in accordance with a bus protocol.
23. The device of claim 22, wherein the protocol comprises an address-before-data protocol.
24. The device of claim 16, wherein each of the first and second integrated circuits further comprises a plurality of functional blocks each coupled to the bus.
25. The device of claim 24, wherein the first and second stimulation circuitry blocks and the plurality of functional blocks on the first and second integrated circuits each couple to a communication bus using bus interface circuitry.
Type: Application
Filed: Sep 16, 2010
Publication Date: Jan 20, 2011
Applicant: BOSTON SCIENTIFIC NEUROMODULATION CORPORATION (Valencia, CA)
Inventors: Paul J. Griffith (Moorpark, CA), Jordi Parramon (Valencia, CA), Goran N. Marnfeldt (Hollviken), Daniel Aghassisn (Los Angeles, CA), Kiran Nimmagadda (Valencia, CA), Emanuel Feldman (Simi Valley, CA), Jess W. Shi (Winnetka, CA)
Application Number: 12/883,797
International Classification: A61N 1/08 (20060101);