Patents by Inventor Paul Kohl

Paul Kohl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040180465
    Abstract: A method of fabricating an electrostatic actuator with an intrinsic stress gradient is provided. An electrode is formed on a substrate and a support layer is formed over the electrode. A metal layer is deposited onto the support layer via a deposition process. Deposition process conditions are varied in order to induce a stress gradient into the metal layer. The intrinsic stress in the metal layer increases in the direction from the bottom to the top of the metal layer. The support layer under the electrode is removed to release the electrostatic actuator.
    Type: Application
    Filed: September 22, 2003
    Publication date: September 16, 2004
    Applicant: Superconductor Technologies, Inc.
    Inventors: Jurgen Musolf, Paul Kohl
  • Patent number: 6788867
    Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: September 7, 2004
    Assignee: Georgia Tech Research Corp.
    Inventors: Tony Mule′, James D. Meindl, Paul Kohl, Stephen M. Schultz, Thomas K. Gaylord, Elias N. Glytsis, Ricardo Villalaz, Muhannad Bakir, Hollie Reed
  • Patent number: 6785458
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: August 31, 2004
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule′, Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Publication number: 20040146803
    Abstract: Polymers, methods of use thereof, and methods of decomposition thereof, are provided. One exemplary polymer, among others, includes, a composition having a sacrificial polymer and a photoacid generator.
    Type: Application
    Filed: October 31, 2003
    Publication date: July 29, 2004
    Inventors: Paul A. Kohl, Paul Jayachandran Joseph, Hollie Reed, Sue Bidstrup-Allen, Celesta E. White, Clifford Henderson
  • Publication number: 20040131829
    Abstract: Microstructures and methods of fabricating microstructures are disclosed. One exemplary microstructure, among others, includes a substrate, an overcoat layer disposed upon the substrate, an air-region within at least a portion of the overcoat layer, and a framing material layer engaging at least a portion of the air-region on the inside of the framing material layer and engaging the overcoat layer on the outside of the framing material layer.
    Type: Application
    Filed: October 28, 2003
    Publication date: July 8, 2004
    Inventors: Paul Jayachandran Joseph, Paul A. Kohl, Sue Ann Bidstrup Allen
  • Publication number: 20040132855
    Abstract: Polymers, methods of use thereof, and methods of decomposition thereof, are provided. One exemplary polymer, among others, includes, a photodefinable polymer having a sacrificial polymer and a photoinitiator.
    Type: Application
    Filed: October 16, 2003
    Publication date: July 8, 2004
    Inventors: Paul A. Kohl, SueAnn Bidstrup Allen, Xiaoqun Wu, Clifford Lee Henderson
  • Publication number: 20040126076
    Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.
    Type: Application
    Filed: December 11, 2003
    Publication date: July 1, 2004
    Inventors: Tony Mule, James D. Meindl, Paul Kohl, Stephen M. Schultz, Thomas K. Gaylord, Elias N. Glytsis, Ricardo Villalaz, Muhannad Bakir, Hollie Reed
  • Publication number: 20040086656
    Abstract: Electroless copper plating solutions and methods of use thereof are disclosed. A representative electroless copper plating solution includes a reducing agent that is a source of hypophosphite ions and at least one accelerator compound that accelerates the rate of copper deposition.
    Type: Application
    Filed: November 6, 2002
    Publication date: May 6, 2004
    Inventors: Paul A. Kohl, Jun Li
  • Patent number: 6690081
    Abstract: Devices and method of fabrication thereof are disclosed. A representative device includes one or more lead packages. The lead packages include a substrate including a plurality of die pads, an overcoat polymer layer, a plurality of sacrificial polymer layers disposed between the substrate and the overcoat polymer layer, and a plurality of leads. Each lead is disposed upon the overcoat polymer layer having a first portion disposed upon a die pad. The sacrificial polymer layer can be removed to form one or more air-gaps.
    Type: Grant
    Filed: November 19, 2001
    Date of Patent: February 10, 2004
    Assignee: Georgia Tech Research Corporation
    Inventors: Muhannad S. Bakir, Hollie Reed, Paul Kohl, Chirag S. Patel, Kevin P. Martin, James Meindl
  • Patent number: 6625004
    Abstract: An electrostatic actuator with an intrinsic stress gradient is provided. The electrostatic actuator comprises an electrode and an electrostatically actuated beam fixed at one end relative to the electrode. The electrostatically actuated beam further includes a metal layer made substantially of a single metal with an induced stress gradient therein. The stress gradient in the metal layer determines the initial curvature of the beam. Upon electrostatic actuation of the beam, the beam is deflected from its initial curvature relative to the electrode. In one embodiment, the electrostatically actuated beam is used as a top movable electrode of an electrostatically actuated variable capacitor. The capacitance of the electrostatically actuated capacitor is changed upon electrostatic actuation of the beam.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: September 23, 2003
    Assignee: Superconductor Technologies, Inc.
    Inventors: Jurgen Musolf, Paul Kohl
  • Patent number: 6509386
    Abstract: A method of forming a porous insulating composition comprising the steps of (A) providing at least one organic sacrificial material/dielectric material composition comprising at least one organic sacrificial material and at least one dielectric material; and (B) removing the at least one organic sacrificial material in the at least one organic sacrificial material/dielectric material composition, in order to generate pores in the at least one dielectric material. Also disclosed is a composition useful in making a porous insulator, comprising a heat-activated, pore-forming, sacrificial material; and a dielectric material. Alternatively, the composition useful in making a porous insulator, comprises at least one pore-forming, organic sacrificial material; and at least one dielectric material, wherein the at least one pore-forming, material is a norbornene-type polymer.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: January 21, 2003
    Assignee: Georgia Tech Research Corporation
    Inventor: Paul A. Kohl
  • Publication number: 20030012539
    Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.
    Type: Application
    Filed: April 29, 2002
    Publication date: January 16, 2003
    Inventors: Tony Mule', James D. Meindl, Paul Kohl, Stephen M. Schultz, Thomas K. Gaylord, Elias N. Glytsis, Ricardo Villalaz, Muhannad Bakir, Hollie Reed
  • Publication number: 20020186950
    Abstract: Waveguides and methods of fabrication thereof are presented. A representative waveguide includes a waveguide core and a cladding layer, where the cladding layer surrounds the waveguide core. The waveguide core and cladding can be made of a host material having a plurality of nano-pores, wherein the nano-pores include a sacrificial material, and the sacrificial material can be selectively decomposed in both the core and cladding layers to form a plurality of nano air-gaps.
    Type: Application
    Filed: May 10, 2002
    Publication date: December 12, 2002
    Inventors: Tony Mule', Paul Kohl, James D. Meindl, Agnes Padovani, Thomas K. Gaylord, Elias N. Glytsis, Sue Ann B. Allen
  • Patent number: 6469761
    Abstract: The present invention enables efficient microfabrication of a fully integrated liquid crystal display device. Initially, a sacrificial layer is formed on a substrate that has conductive pads connected thereto. The sacrificial layer is patterned, and portions of the sacrificial layer are removed to expose portions of the underlying layer supporting the sacrificial layer. Then, a permeable layer is formed on the sacrificial layer, thereby filling in the space vacated by the removed potions of the sacrificial layer. The structure is heated and the material of the sacrificial layer is allowed to dissolve into and dissipate through the permeable layer in order to leave a cavity. Once the sacrificial layer is removed, the permeable layer is supported by the portion of the permeable layer filling in the space vacated by the removed portions of the sacrificial layer.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: October 22, 2002
    Assignee: Georgia Tech Research Corp.
    Inventors: Timothy J. Drabik, Paul A. Kohl
  • Publication number: 20020136481
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Application
    Filed: February 11, 2002
    Publication date: September 26, 2002
    Inventors: Tony Mule', Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Publication number: 20020127768
    Abstract: Devices and method of fabrication thereof are disclosed. A representative device includes one or more lead packages. The lead packages include a substrate including a plurality of die pads, an overcoat polymer layer, a plurality of sacrificial polymer layers disposed between the substrate and the overcoat polymer layer, and a plurality of leads. Each lead is disposed upon the overcoat polymer layer having a first portion disposed upon a die pad. The sacrificial polymer layer can be removed to form one or more air-gaps.
    Type: Application
    Filed: November 19, 2001
    Publication date: September 12, 2002
    Inventors: Muhannad S. Badir, Hollie Reed, Paul Kohl, Chirag S. Patel, Kevin P. Martin, James Meindl
  • Publication number: 20020122648
    Abstract: Waveguides having air-gap cladding layers and methods of fabricating waveguides having air-gap cladding layers are disclosed. A representative waveguide includes a waveguide core having an air-gap cladding layer engaging a portion of the waveguide core. In addition, a representative method of fabricating a waveguide having an air-gap cladding layer includes: providing a substrate having a lower cladding layer disposed on the substrate; disposing a waveguide core on a portion of the lower cladding layer; disposing a sacrificial layer onto at least one portion of the lower cladding layer and the waveguide core; disposing an overcoat layer onto the lower cladding layer and the sacrificial layer; and removing the sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and engaging a portion of the waveguide core.
    Type: Application
    Filed: February 11, 2002
    Publication date: September 5, 2002
    Applicant: Georgia Tech Research Corporation
    Inventors: Tony Mule', James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Paul Kohl
  • Patent number: 6165890
    Abstract: A method of forming an air gap or gaps within solid structures and specifically semiconductor structures to reduce capacitive coupling between electrical elements such as metal lines, wherein a norbornene-type polymer is used as a sacrificial material to occupy a closed interior volume in a semiconductor structure. The sacrificial material is caused to decompose into one or more gaseous decomposition products which are removed, preferably by diffusion, through an overcoat layer. The decomposition of the sacrificial material leaves an air gap or gaps at the closed interior volume previously occupied by the norbornene-type polymer. The air gaps may be disposed between electrical leads to minimize capacitive coupling therebetween.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: December 26, 2000
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul A. Kohl, Qiang Zhao, Sue Ann Bidstrup Allen
  • Patent number: 6162838
    Abstract: A method of forming a porous insulating composition comprising the steps of (A) providing at least one organic sacrificial material/dielectric material composition comprising at least one organic sacrificial material and at least one dielectric material; and (B) removing the at least one organic sacrificial material in the at least one organic sacrificial material/dielectric material composition, in order to generate pores in the at least one dielectric material. Also disclosed is a composition useful in making a porous insulator, comprising a heat-activated, pore-forming, sacrificial material; and a dielectric material. Alternatively, the composition useful in making a porous insulator, comprises at least one pore-forming, organic sacrificial material; and at least one dielectric material, wherein the at least one pore-forming, material is a norbornene-type polymer.
    Type: Grant
    Filed: June 4, 1999
    Date of Patent: December 19, 2000
    Assignee: Georgia Tech Research Corporation
    Inventor: Paul A. Kohl
  • Patent number: 6141072
    Abstract: The present invention enables efficient microfabrication of a fully integrated liquid crystal display device. Initially, a sacrificial layer is formed on a substrate that has conductive pads connected thereto. The sacrificial layer is patterned, and portions of the sacrificial layer are removed to expose portions of the underlying layer supporting the sacrificial layer. Then, a permeable layer is formed on the sacrificial layer, thereby filling in the space vacated by the removed potions of the sacrificial layer. The structure is heated and the material of the sacrificial layer is allowed to dissolve into and dissipate through the permeable layer in order to leave a cavity. Once the sacrificial layer is removed, the permeable layer is supported by the portion of the permeable layer filling in the space vacated by the removed portions of the sacrificial layer.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: October 31, 2000
    Assignee: Georgia Tech Research Corporation
    Inventors: Timothy J. Drabik, Paul A. Kohl