Abstract: A MOSFET gate or a MOSFET source or drain region comprises silicon germanium or polycrystalline silicon germanium. Silicidation with nickel is performed to form a nickel germanosilicide that preferably comprises the monosilicide phase of nickel silicide. The inclusion of germanium in the silicide provides a wider temperature range within which the monosilicide phase may be formed, while essentially preserving the superior sheet resistance exhibited by nickel monosilicide. As a result, the nickel germanosilicide is capable of withstanding greater temperatures during subsequent processing than nickel monosilicide, yet provides approximately the same sheet resistance and other beneficial properties as nickel monosilicide.

Abstract: A method for forming a copper interconnect with improved via integrity and elimination of via voiding employs a copper seed layer having an alloy element within the seed layer. The alloy element increases the resistance of the copper seed layer to acidic plating chemistry as the vias are filled and as the pulse-reverse wave form is initiated in the electrochemical plating process. The prevention of void formations at the bottom of the via improves the copper filling, with resulting improved electromigration performance, reduced via resistance and improved product speed.

Abstract: A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into the barrier material layer, and implanting a second alloy element after deposition of the via material. The implanted first alloy element makes the barrier material layer more resistant to copper diffusion. The implanted second alloy element diffuses to a top interface of the via material and reduces bulk diffusion from the via material.

Abstract: A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and forming an implanted layer proximate and conformal to the barrier layer and the seed layer. The via aperture is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer.

Abstract: The reliability and electromigration resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer with at least one alloying element for the metal of the feature, and then uniformly diffusing at least a minimum amount of the at least one alloying element of the at least one thin layer for a predetermined minimum depth below the upper surface of the features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer.

Abstract: A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and forming an implanted layer proximate and conformal to the barrier layer and the seed layer. The via aperture is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer.

Abstract: A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via. The via aperture is configured to receive the ternary copper alloy via material and electrically connect a first conductive layer and a second conductive layer. The ternary copper alloy via material helps the via to have a lower resistance and an increased grain size with staffed grain boundaries.

Abstract: A metal gate structure and method of forming the same employs an etch stop layer between a first metal layer, made of TiN, for example, and the metal gate formed of tungsten. The etch stop layer prevents overetching of the TiN during the etching of the tungsten in the formation of the metal gate. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum in the etch stop layer allows a thin etch stop layer to be used that provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.

Abstract: A method of forming ultra-shallow junctions in a semiconductor wafer forms the gate and source/drain junctions having upper surfaces at first metal suicide regions on the gate and source/drain junctions. These first metal silicide regions have a higher resistivity. Amorphous silicon is deposited on the first metal suicide regions by plasma enhanced chemical vapor deposition (PECVD). The PECVD process may be a lower pressure deposition process, performed at multiple stations to form the amorphous silicon layer in multiple layers. This creates a more uniform amorphous silicon layer across the wafer and different patterning densities, thereby improving device performance and characteristics. Annealing is then performed to form second metal silicide regions of a lower resistivity, by diffusion reaction of the first metal silicide regions and the amorphous silicon that was deposited by the PECVD process.

Abstract: Excessive variation in vertical (i.e., inter-level) capacitance of multi-level metallization semiconductor devices resulting in racing of clock skew circuitry of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, are simultaneously eliminated, or substantially reduced, by selectively providing an etch-resistant masking material at thinner, i.e., recessed, portions of a first, low k gap fill material blanket-deposited over spaced-apart features of a metallization pattern and in the spaces therebetween. The surfaces of thicker, non-recessed portions thereof are etched so as to be substantially co-planar with the feature surfaces and the recessed portions. The etch-resistant mask is then removed, and second, oxide-based and third, low k dielectric layers deposited over the planarized surface.

Abstract: Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.

Abstract: A metal gate structure and method of forming the same introduces metal impurities into a first metal layer, made of TiN, for example. The impurities create a surface region of greater etch selectivity that prevents overetching of the TiN during the etching of an overlying tungsten gate during the formation of the metal gate structure. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum as the metal impurities provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.

Abstract: A method of performing a two stage anneal in the formation of an alloy interconnect can include forming a via aperture in a dielectric layer where the via aperture provides an area for formation of a via, providing a seed layer along lateral side walls of the via aperture, rapid thermal annealing the seed layer to facilitate copper grain growth in the via, and slowly annealing the seed layer to facilitate desired distribution of alloy doping. The use of two anneals-one fast (e.g., 60 seconds) at lower temperatures (e.g., 150° C. to 250° C.) and one slow (e.g., minutes to several hours) at higher temperatures (e.g., 200° C. to 450° C.)—helps to control grain growth and alloy doping distribution.

Abstract: A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffusion site below the via in the underlying metal. Once the copper fill is performed in the via, an annealing step allows the alloying element to go into solid solution with the copper in and around the via. The solid solution of the alloying element and copper at the bottom of the via in the copper line improves the electromigration reliability of the structure.

Abstract: A metal interconnect structure and method for making the same provides an alloying elements layer that lines a via in a dielectric layer. The alloying element layer is therefore inserted at a critical electromigration failure site, i.e., at the fast diffusion site below the via in the underlying metal. Once the copper fill is performed in the via, an annealing step allows the alloying element to go into solid solution with the copper in and around the via. The solid solution of the alloying element and copper at the bottom of the via in the copper line improves the electromigration reliability of the structure.

Abstract: A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. A barrier layer is deposited on the PVD amorphous silicon layer. The metal is then formed on the barrier layer. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer. The barrier layer prevents interaction between the PVD amorphous silicon layer and the metal, thereby allowing higher temperature subsequent processing while preserving the work function of the gate.

Abstract: A metal interconnect structure and method of making the same implants ions of an alloy elements into a copper line through a via. Then ion implantation of the alloy elements in the copper line through the via provides improved electromigration properties at the copper line at a critical electromigration failure site, without attempting to provide alloy elements throughout the entire copper line.

Abstract: The present invention is directed to a method of controlling polishing processes based upon x-ray fluorescence measurements. In one illustrative embodiment, the method comprises providing a wafer comprised of a layer of insulating material having a barrier metal layer formed thereabove and a layer of copper formed above the barrier metal layer, performing a chemical mechanical polishing operation to remove the barrier metal layer, irradiating at least one area of the wafer with x-rays, and analyzing x-rays leaving the irradiated area to determine the presence of material comprising the barrier metal layer.

Abstract: A method (M) of determining the effectiveness of a deposited thin conformal barrier layer (30) by forming a test specimen and measuring the copper (Cu) penetration from a metallization layer (40) through the barrier layer (30) (e.g., refractory metals, their nitrides, their carbides, or their other compounds), through a thin insulating dielectric layer (20) (e.g., SiO2), and into a semiconductor (10) substrate (e.g., Si), wherein the interaction between the migrating metal ions and the semiconductor ions are detected/monitored, and wherein the detection/monitoring comprises (1) stripping at least a portion of the insulating dielectric layer (20) and the barrier layer (30) and (2) examining the semiconductor substrate (10) surface of the test specimen, thereby improving interconnect reliability, enhancing electromigration resistance, improving corrosion resistance, reducing copper diffusion, and a test specimen device thereby formed.

Abstract: The present invention is generally directed to a transistor having a gate stack comprised of a metal, and a method of making same. In one illustrative embodiment, the transistor is comprised of a gate stack comprised of a gate insulation layer positioned above a semiconducting substrate, a layer of silicon positioned above the gate insulation layer, a layer of adhesion material positioned above the layer of silicon, a layer of metal positioned above the layer of adhesion material, and a plurality of source/drain regions formed in the substrate adjacent the gate stack.