Patents by Inventor Paul S. Diefenbaugh

Paul S. Diefenbaugh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140267336
    Abstract: Data transmission for display partial update. An embodiment of an apparatus includes a display controller to transfer pixel data from a frame buffer to a video display and to select a granularity of a plurality of granularities for units of data for the transfer of the pixel data, and a detection element to track updates to the frame buffer, the detection element to identify at least a first damage area of the pixel data that has been changed from a previous image, wherein the display controller is to provide the video display with the identified first damage area of the pixel data in more or more units of data of the chosen granularity.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Nithyananda S. Jeganathan, Kyungtae Han, Paul S. Diefenbaugh
  • Patent number: 8823721
    Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques are useful to avoid visual distortions when changing from a first video source to a second video source.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: September 2, 2014
    Assignee: Intel Corporation
    Inventors: Maximino Vasquez, Ravi Ranganathan, Seh W. Kwa, Todd M. Witter, Kyungtae Han, Paul S. Diefenbaugh
  • Publication number: 20140189403
    Abstract: Methods and systems may provide for determining a latency constraint associated with a platform and determine an idle window based on the latency constraint. In addition, a plurality of devices on the platform may be instructed to cease one or more activities during the idle window. In one example, the platform is placed in a sleep state during the idle window.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Eugene Gorbatov, Paul S. Diefenbaugh, John H. Crawford, Anil K. Kumar, Richard J. Greco
  • Publication number: 20140189385
    Abstract: Methods and systems may provide for determining a plurality of buffer-related settings for a corresponding plurality of idle states and outputting the plurality of buffer-related settings to a device on a platform. The device may determine an observed bandwidth for a channel associated with a receive buffer and identify a selection of a buffer-related setting from the plurality of buffer-related settings based at least in part on the observed bandwidth. In one example, each buffer-related setting includes a latency tolerance and a corresponding idle duration.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Inventors: Eugene Gorbatov, Paul S. Diefenbaugh, Eric K. Mann, Jr-Shian Tsai
  • Publication number: 20140189398
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for detecting active and semi-active workloads during execution on a platform processing device and enabling a duty cycle process to reduce thermal output and power consumption, and align unaligned activity. In various embodiments, the duty cycle processing may be enabled during an active workload when thermal output or power consumption is above a thermal threshold or power consumption threshold that is below an efficient operating point for the platform processing device. The duty cycle processing may also be enabled during semi-active workloads when the workload causes the platform processing device to be underutilized and unaligned. The duty cycle processing may comprise enabling a forced idle period for the platform processing device. Other embodiments are described and claimed.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Inventors: EUGENE GORBATOV, PAUL S. DIEFENBAUGH, ANDREW D. HENROID, GUY M. THERIEN
  • Publication number: 20140189694
    Abstract: Methods and systems may provide for identifying a workload associated with a platform and determining a scalability of the workload. Additionally, a performance policy of the platform may be managed based at least in part on the scalability of the workload. In one example, determining the scalability includes determining a ratio of productive cycles to actual cycles.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Inventors: Paul S. Diefenbaugh, Andrew D. Henroid, Eliezer Weissmann, Krishnakanth V. Sistla
  • Publication number: 20140168241
    Abstract: An apparatus may include a memory to store one or more graphics rendering commands in a queue after generation. The apparatus may also include a processor circuit, and a graphics rendering command manager for execution on the processor to dynamically determine at one or more instances a total execution duration for the one or more graphics rendering commands, where the total execution duration comprises a total time to render the one or more graphics rendering commands. The graphics rendering command manager also may be for execution on the processor to generate a signal to transmit the one or more graphics rendering commands for rendering by a graphics processor when the total execution duration exceeds a graphics rendering command execution window.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Inventors: NITHYANANDA S. JEGANATHAN, RAJESH POORNACHANDRAN, PAUL S. DIEFENBAUGH, KYUNGTAE HAN
  • Publication number: 20140132616
    Abstract: A hybrid display frame buffer for a display subsystem. An embodiment of an apparatus a first logic to split a video image into a first data portion and a second data portion; a display frame buffer including a first memory component having a first type of memory and a second memory component having a second type of memory, the first logic to write the first data portion to the first memory component and the second data portion to the second memory component; and a second logic to read the first data portion from the first memory component and the second data component from the second memory component, and to combine the first data portion and the second data portion to generate a combined video image.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Inventors: Kyungtae Han, Paul S. Diefenbaugh, Taemin Kim, Nithyananda S. Jeganathan, Sameer Abhinkar
  • Patent number: 8689028
    Abstract: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: April 1, 2014
    Assignee: Intel Corporation
    Inventors: Paul S. Diefenbaugh, Robert E. Gough, Yuval Bachrach, Mikal C. Hunsaker, Rafi Ben-Tal, Ilan Pardo, Gideon Prat, David J. Harriman
  • Patent number: 8643658
    Abstract: Techniques are described that can used to synchronize the start of frames from multiple sources so that when a display is to output a frame to a next source, boundaries of current and next source are aligned. Techniques attempt to avoid visible glitches when switching from displaying a frame from a first source to displaying frames from a second source even though alignment is achieved by switching if frames that are to be displayed from the second source are similar to those displayed from the first source.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: February 4, 2014
    Assignee: Intel Corporation
    Inventors: Seh Kwa, Maximino Vasquez, Ravi Ranganathan, Todd M. Witter, Kyungtae Han, Paul S. Diefenbaugh
  • Patent number: 8631257
    Abstract: Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: January 14, 2014
    Assignee: Intel Corporation
    Inventors: Jaya L. Jeyaseelan, Neil Songer, Barnes Cooper, Paul S. Diefenbaugh
  • Publication number: 20130283032
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Application
    Filed: December 30, 2011
    Publication date: October 24, 2013
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem
  • Publication number: 20130275796
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Application
    Filed: December 30, 2011
    Publication date: October 17, 2013
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
  • Publication number: 20130275737
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Application
    Filed: December 30, 2011
    Publication date: October 17, 2013
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
  • Publication number: 20130007486
    Abstract: A method and system for determining an energy-efficient operating point of the platform or system. The platform has logic to dynamically manage setting(s) of the processing cores and/or platform components in the platform to achieve maximum system energy efficiency. By using the characteristics of the workload and/or platform to determine the optimum settings of the platform, the logic of the platform facilitates performance guarantees of the platform while minimizing the energy consumption of the processor core and/or platform. The logic of the platform identifies opportunities to run the processing cores at higher performance levels which decreases the execution time of the workload and transitions the platform to a low-power system idle state after the completion of the execution of the workload. Since the execution time of the workload is reduced, the platform spends more time in the low-power system idle state and therefore the overall system energy consumption is reduced.
    Type: Application
    Filed: February 29, 2012
    Publication date: January 3, 2013
    Inventors: Andrew D. Henroid, Eugene Gorbatov, Paul S. Diefenbaugh
  • Publication number: 20130007483
    Abstract: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Inventors: Paul S. Diefenbaugh, Robert E. Gough, Yuval Bachrach, Mikal C. Hunsaker, Rafi Ben-Tal, Ilan Pardo, Gideon Prat, David J. Harriman
  • Publication number: 20120254645
    Abstract: Control of platform control of platform power consumption using selective updating of a display image. An embodiment of an apparatus includes a display controller to transfer pixel data from a frame buffer to a video display and a detection element to track updates to the frame buffer, the detection element to identify a portion of the pixel data that has been changed from a previous image, where the display controller is to provide the video display with the identified portion of the pixel data.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Inventors: Nithyananda S. Jeganathan, Paul S. Diefenbaugh, Kyungtae Han, Jinjun Liu, James A. Bish, Paul C. Drews
  • Publication number: 20120198248
    Abstract: Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
    Type: Application
    Filed: April 12, 2012
    Publication date: August 2, 2012
    Inventors: Jaya L. Jeyaseelan, Neil Songer, Barnes Cooper, Paul S. Diefenbaugh
  • Patent number: 8185758
    Abstract: A method and system for determining an energy-efficient operating point of the platform or system. The platform has logic to dynamically manage setting(s) of the processing cores and/or platform components in the platform to achieve maximum system energy efficiency. By using the characteristics of the workload and/or platform to determine the optimum settings of the platform, the logic of the platform facilitates performance guarantees of the platform while minimizing the energy consumption of the processor core and/or platform. The logic of the platform identifies opportunities to run the processing cores at higher performance levels which decreases the execution time of the workload and transitions the platform to a low-power system idle state after the completion of the execution of the workload. Since the execution time of the workload is reduced, the platform spends more time in the low-power system idle state and therefore the overall system energy consumption is reduced.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventors: Andrew D. Henroid, Eugene Gorbatov, Paul S. Diefenbaugh
  • Patent number: 8176341
    Abstract: Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 8, 2012
    Assignee: Intel Corporation
    Inventors: Jaya L. Jeyaseelan, Neil Songer, Barnes Cooper, Paul S. Diefenbaugh