Abstract: In one example, an apparatus includes storage to store instructions executable by at least one processor, and at least one processor to execute the instructions. When executed, the instructions cause at least one processor to determine a first connection made between a display content transmitting device and a display content receiving device. In response to the determined first connection, the instructions also cause the at least one processor to activate a second connection between the display content transmitting device and the display content receiving device, to pause the second connection, to determine a deactivation of the first connection, to un-pause the second connection in response to the deactivation of the first connection, and to stream display content from the transmitting device to the receiving device via the second connection.

Abstract: A method and apparatus for buffering data to enable longer reduced power consumption state residency are described. In one embodiment, a computing system comprises a first device operable in one or more reduced power consumption states and a non-reduced power consumption state; one or more I/O devices operable to generate data to be forwarded to the first device; and a write buffer coupled to the first device and the one or more I/O devices to temporarily store data received from one or more I/O devices when the first device is in one of the one or more reduced power consumption states.

Abstract: Described is an apparatus comprising a first circuitry and a second circuitry. The first circuitry may be operable to provide output to a unidirectional data path for carrying a packetized data stream. The second circuitry may be operable to provide output to, and obtain input from, a bidirectional control path for carrying a packetized control stream. The packetized data stream may comprise pixel data traffic and frame-synchronous metadata traffic, and the packetized control stream may comprise frame-asynchronous metadata traffic and control traffic.

Abstract: Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.

Abstract: Computing devices and techniques for managing transmission and display of a display data stream are described. In one embodiment, for example, an apparatus may include at least one memory and logic for a display source, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to generate display information comprising at least one frame for presentation at a display panel operably coupled to a display sink, receive display sink information indicating a space availability of a buffer of the display sink, the buffer to store at least a portion of the display information, and provide the display information to the display sink based on the display sink information. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

Abstract: In one example, a head mounted display system includes detecting a position of a head of a user of the head mounted display, predicting a position of the head of the user of the head mounted display at a time after a time that the position of the head of the user was detected, and rendering image data based on the predicted head position.

Abstract: Systems and methods may provide for receiving unfiltered feedback information from a network interface component of a wireless display pipeline and receiving display region-specific information from a region update component of the wireless display pipeline. Additionally, a coding policy associated with wireless display content may be adjusted based on the unfiltered feedback information and the display region-specific information.

Abstract: Source devices are provided that increase quality of displayed images by dynamically integrating higher fidelity update frames into a base stream encoded using an encoding technique (e.g., chroma-subsampling and/or another lossless encoding technique). Use of base image frames enables backward compatibility with existing technology and serves as a baseline for bandwidth scaling. The fidelity update frames may include raw image data, lossy, or losslessly compressed image data, and/or additional subsampled image data. The image data included in the fidelity update frames may apply to the entire base image frame or a portion thereof. The fidelity update frames may include incremental data or complete, high fidelity image data for a portion of an entire image. The source devices may store and implement fidelity management policies that control operation of the devices to balance resource consumption against fidelity to meet the needs of specific operational environments.

Abstract: Sink devices are provided that increase quality of displayed images by dynamically integrating higher fidelity update frames into a base stream encoded using an encoding technique (e.g., chroma-subsampling and/or another lossless encoding technique). Use of base image frames enables backward compatibility with existing technology and serves as a baseline for bandwidth scaling. The fidelity update frames may include raw image data, lossy, or losslessly compressed image data, and/or additional subsampled image data. The image data included in the fidelity update frames may apply to the entire base image frame or a portion thereof. The fidelity update frames may include incremental data or complete, high fidelity image data for a portion of an entire image. The sink devices may store and implement fidelity management policies that control operation of the devices to balance resource consumption against fidelity to meet the needs of specific operational environments.

Abstract: Methods, apparatuses and systems may provide for a video transmitter that generates a primary bitstream based on a video signal, wherein the primary bitstream is encoded with subsampled chroma information, and detects a static condition with respect to the video signal. Additionally, a plurality of auxiliary bitstreams may be generated, in response to the static condition, based on the video signal. Each of the plurality of auxiliary bitstreams may be encoded with full resolution chroma information. In one example, a video receiver may detect that the auxiliary bitstreams are associated with the primary bitstream, decode the primary bitstream and the plurality of auxiliary bitstreams to obtain luma information and the full resolution chroma information, and multiplex the luma information with the full resolution chroma information.

Abstract: Techniques related to encoding image content for transmission and display via a remote device with improved latency and efficiency are discussed. Such techniques may include skipping one or more of frame capture, encode, packetization, and transmission for a frame based on a skip indicator. One or more selective updates may be captured for the skipped frame and integrated into an encode of a subsequent non-skipped frame, which may be packetized and transmitted for to the remote device for presentment to a user.

Abstract: Technologies for input compute offloading of digital content include a source computing device for wirelessly transmitting the digital content to a destination computing device. The destination computing device is configured to detect inputs initiated by a user on a display of the destination computing device and transmit input characteristics to the source computing device that are usable by the source computing device to render the digital content to include one or more objects based on the one or more input characteristics. The source computing device is configured to receive the input characteristics from the destination computing device and render the digital content to include one or more objects based on the one or more input characteristics. Other embodiments are described and claimed.

Abstract: Examples are disclosed for composing memory resources across devices. In some examples, memory resources associated with executing one or more applications by circuitry at two separate devices may be composed across the two devices. The circuitry may be capable of executing the one or more applications using a two-level memory (2LM) architecture including a near memory and a far memory. In some examples, the near memory may include near memories separately located at the two devices and a far memory located at one of the two devices. The far memory may be used to migrate one or more copies of memory content between the separately located near memories in a manner transparent to an operating system for the first device or the second device. Other examples are described and claimed.

Abstract: An apparatus, system, and method, the method including receiving an indication of a idle state capability of a platform connected device; determining, by a chipset, an idle power state compatible with the device; and directing the device to enter the determined idle power state based on a power state of the chipset.

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.

Abstract: A tile concept allows independent encoding and decoding of regions of the video frames combined with changes in the way that the coded tiles are packetized and queued for transport. After the coded tile network abstraction layer (NAL) units are packetized into MPEG-TS frames, the more important tile data is put in the network abstraction layer at the head of the queue while the less important data is inserted later in the queue. Audio can also be accorded high priority. For a given link bandwidth/latency environment, the important data is transmitted first and the less important data can be discarded at the transmitter with less impact on the user perceived quality.

Abstract: A higher frame rate (a multiple of the original display frame rate at the host) is exploited at a display sink device to opportunistically insert new decoded frames for display at the higher refresh rate of the sink. In other words, delayed frames arriving at the sink may get a chance to be displayed during the higher refresh rate cycle, thus offering a better (“smoother”) viewing experience along with improved interactivity or “responsiveness.

Abstract: An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.