Patents by Inventor Paul W. Sanders
Paul W. Sanders has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9871008Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.Type: GrantFiled: November 4, 2016Date of Patent: January 16, 2018Assignee: NXP USA, INC.Inventors: Paul W. Sanders, Wayne R. Burger, Thuy B. Dao, Joel E. Keys, Michael F. Petras, Robert A. Pryor, Xiaowei Ren
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Patent number: 9837299Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates. An active device (AD) substrate has contacts on its upper portion. A ground plane is located between the AD substrate and an IPD substrate. The ground plane provides superior IPD to AD cross-talk attenuation.Type: GrantFiled: May 30, 2017Date of Patent: December 5, 2017Assignee: INVENSAS CORPORATIONInventors: Paul W. Sanders, Robert E. Jones, Michael F. Petras, Chandrasekaram Ramiah
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Publication number: 20170301577Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates. An active device (AD) substrate has contacts on its upper portion. A ground plane is located between the AD substrate and an IPD substrate. The ground plane provides superior IPD to AD cross-talk attenuation.Type: ApplicationFiled: May 30, 2017Publication date: October 19, 2017Applicant: Invensas CorporationInventors: Paul W. SANDERS, Robert E. JONES, Michael F. PETRAS, Chandrasekaram RAMIAH
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Patent number: 9698131Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.Type: GrantFiled: December 21, 2015Date of Patent: July 4, 2017Assignee: Invensas CorporationInventors: Paul W. Sanders, Robert E. Jones, Michael F. Petras, Chandrasekaram Ramiah
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Publication number: 20170077051Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.Type: ApplicationFiled: November 4, 2016Publication date: March 16, 2017Inventors: Paul W. Sanders, Wayne R. Burger, Thuy B. Dao, Joel E. Keys, Michael F. Petras, Robert A. Pryor, Xiaowei Ren
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Patent number: 9508599Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face (63) of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.Type: GrantFiled: April 22, 2015Date of Patent: November 29, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Paul W. Sanders, Wayne R. Burger, Thuy B. Dao, Joel E. Keys, Michael F. Petras, Robert A. Pryor, Xiaowei Ren
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Publication number: 20160111404Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.Type: ApplicationFiled: December 21, 2015Publication date: April 21, 2016Inventors: Paul W. Sanders, Robert E. Jones, Michael F. Petras, Chandrasekaram RAMIAH
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Patent number: 9236365Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.Type: GrantFiled: May 12, 2014Date of Patent: January 12, 2016Assignee: Invensas CorporationInventors: Paul W. Sanders, Robert E. Jones, Michael F. Petras, Chandrasekaram Ramiah
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Publication number: 20150228545Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates and lower resistance inductors for the IC. This eliminates significant in-substrate electromagnetic coupling losses from planar inductors and interconnections overlying the substrate. The active transistor(s) are formed in the substrate proximate the front face. Planar capacitors are also formed over the front face (63) of the substrate. Various terminals of the transistor(s), capacitor(s) and inductor(s) are coupled to a ground plane on the rear face of the substrate using through-substrate-vias to minimize parasitic resistance. Parasitic resistance associated with the planar inductors and heavy current carrying conductors is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance.Type: ApplicationFiled: April 22, 2015Publication date: August 13, 2015Inventors: PAUL W. SANDERS, WAYNE R. BURGER, THUY B. DAO, JOEL E. KEYS, MICHAEL F. PETRAS, ROBERT A. PRYOR, XIAOWEI REN
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Patent number: 9064712Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44?, 45?) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1?, 52-1?, 94, 94?, 94?) overlying the substrate (60). The active transistor(s) (41?) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42?, 43?) are also formed over the front face (63) of the substrate (60). Various terminals (42-1?, 42-2?, 43-1, 43-2?,50?, 51?, 52?, 42-1?, 42-2?, etc.) of the transistor(s) (41?), capacitor(s) (42?, 43?) and inductor(s) (44?, 45?) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98?) to minimize parasitic resistance.Type: GrantFiled: August 12, 2010Date of Patent: June 23, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventors: Paul W. Sanders, Wayne R. Burger, Thuy B. Dao, Joel E. Keys, Michael F. Petras, Robert A. Pryor, Xiaowei Ren
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Publication number: 20140332980Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.Type: ApplicationFiled: May 12, 2014Publication date: November 13, 2014Applicant: Invensas CorporationInventors: Paul W. Sanders, Robert E. Jones, Michael F. Petras
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Patent number: 8722459Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.Type: GrantFiled: December 31, 2012Date of Patent: May 13, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Paul W. Sanders, Robert E. Jones, Michael F. Petras
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Patent number: 8628781Abstract: Provided herein are polypeptides comprising or consisting essentially of a QSYDNTLSGSYVF (SEQ ID NO:1) or LSADSSGSYLYVF (SEQ ID NO:2) amino acid sequence. Also provided herein are methods of treating or preventing cast nephropathy in a subject. The methods comprise identifying a subject with or at risk of developing cast nephropathy and administering to the subject any of the polypeptides disclosed herein.Type: GrantFiled: April 1, 2011Date of Patent: January 14, 2014Assignees: The UAB Research Foundation, The United States of America, as Represented by the Department of Veterans AffairsInventor: Paul W. Sanders
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Patent number: 8518764Abstract: A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.Type: GrantFiled: October 24, 2011Date of Patent: August 27, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Thuy B. Dao, Joel E. Keys, Hernan A. Rueda, Paul W. Sanders
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Publication number: 20130129714Abstract: Provided herein are polypeptides comprising or consisting essentially of a QSYDNTLSGSYVF (SEQ ID NO:1) or LSADSSGSYLYVF (SEQ ID NO:2) amino acid sequence. Also provided herein are methods of treating or preventing cast nephropathy in a subject. The methods comprise identifying a subject with or at risk of developing cast nephropathy and administering to the subject any of the polypeptides disclosed herein.Type: ApplicationFiled: April 1, 2011Publication date: May 23, 2013Applicant: THE UAB RESEARCH FOUNDATIONInventor: Paul W. Sanders
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Publication number: 20130099312Abstract: A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.Type: ApplicationFiled: October 24, 2011Publication date: April 25, 2013Inventors: Thuy B. Dao, Joel E. Keys, Hernan A. Rueda, Paul W. Sanders
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Patent number: 8344503Abstract: 3-D ICs (18, 18?, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20).Type: GrantFiled: November 25, 2008Date of Patent: January 1, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Paul W. Sanders, Robert E. Jones, Michael F. Petras, Chandrasekaram Ramiah
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Patent number: 8329579Abstract: Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ?40, usefully ?10 and preferably ?5.Type: GrantFiled: July 21, 2011Date of Patent: December 11, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Paul W. Sanders, Michael F. Petras, Chandrasekaram Ramiah
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Patent number: 8283207Abstract: Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.Type: GrantFiled: March 8, 2011Date of Patent: October 9, 2012Assignee: Freescale Semiconductors, Inc.Inventors: Chandrasekaram Ramiah, Douglas G. Mitchell, Michael F. Petras, Paul W. Sanders
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Publication number: 20120037969Abstract: Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ?100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44?, 45?) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1?, 52-1?, 94, 94?, 94?) overlying the substrate (60). The active transistor(s) (41?) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42?, 43?) are also formed over the front face (63) of the substrate (60). Various terminals (42-1?, 42-2?, 43-1, 43-2?,50?, 51?, 52?, 42-1?, 42-2?, etc.) of the transistor(s) (41?), capacitor(s) (42?, 43?) and inductor(s) (44?, 45?) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98?) to minimize parasitic resistance.Type: ApplicationFiled: August 12, 2010Publication date: February 16, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Paul W. Sanders, Wayne R. Burger, Thuy B. Dao, Joel E. Keys, Michael F. Petras, Robert A. Pryor, Xiaowei Ren