Abstract: A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.

Abstract: An under bump metallurgy (UBM) structure formed over a bond pad and for use in conjunction with a solder ball, provides an upper copper layer over a subjacent composite film that includes a nickel film over a further copper film over a titanium film. One or more reflow operations are used to form a molten solder ball and conditions are selected to ensure that all of the copper from the upper copper layer is dissolved within the molten solder. For SnAg leadfree solder, this leads to the formation of SnAgCu-like leadfree solder. The resulting interface between the solder ball and the nickel layer includes regularly spaced Cu6Sn5 nodules as intermetallics but is free of Ni3Sn4 which can spall into the molten solder causing reliability problems.

Abstract: A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.

Abstract: A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.

Abstract: A thermally-enhanced cavity down ball grid array (CDBGA) package is provided. In one embodiment, the CDBGA package comprises a heat dissipating substrate having a heat spreader and a chip carrier, the chip carrier having a cavity therethrough to allow a chip to be attached to the heat spreader. A chip having an active surface and a corresponding back surface, has the back surface of the chip mounted on the heat spreader. A dummy chip is attached to the active surface of the chip. The dummy chip has a coefficient of thermal expansion approximately equal to the coefficient of thermal expansion of the chip. An encapsulant encapsulates the chip and portions of the dummy chip. Dummy chip 90 has a coefficient of thermal expansion (CTE) approximately equal to the coefficient of thermal expansion of the chip 40.

Abstract: Described is a semiconductor device having improved semiconductor bond pad reliability and methods of manufacturing thereof. The semiconductor device includes a layer formed over an integrated circuit on a semiconductor substrate. The first layer includes a conductive portion and an insulating portion. A second layer is then formed over the first layer and includes a conductive portion corresponding to the first layer's conductive portion and an insulating portion corresponding to the first layer's insulating portion. A bond pad is then formed over the first and second layers such that the bond pad is substantially situated above the conductive portions and the insulating portions of the first and second layers. A bonding ball is then formed on the bond pad substantially above the conduction portion of the first and second layers.

Abstract: A ball grid array (BGA) package having a thermally enhanced dummy chip is provided. In one embodiment, the package comprises a substrate. A chip is attached to the substrate. A heat spreader is disposed over the chip, and a dummy chip is disposed between the heat spreader and the chip. In one embodiment, the dummy chip is pre-attached to the heat spreader prior to placement in the BGA package. With the coefficient of thermal expansion (CTE) of the dummy chip being approximately equal to the CTE of the chip, the stress in the BGA package is reduced, thereby reducing interface delamination among the components of the BGA package.

Abstract: Described is a semiconductor device having improved semiconductor bond pad reliability and methods of manufacturing thereof. The semiconductor device includes a layer formed over an integrated circuit on a semiconductor substrate. The first layer includes a conductive portion and an insulating portion. A second layer is then formed over the first layer and includes a conductive portion corresponding to the first layer's conductive portion and an insulating portion corresponding to the first layer's insulating portion. A bond pad is then formed over the first and second layers such that the bond pad is substantially situated above the conductive portions and the insulating portions of the first and second layers. A bonding ball is then formed on the bond pad substantially above the conduction portion of the first and second layers.

Abstract: A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.

Abstract: A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.

Abstract: Non-cavity semiconductor packages. One embodiment of the packages includes a non-cavity substrate, a first die, an encapsulant, and a second die. The non-cavity substrate comprises a first surface and an opposite second surface. The first surface comprises an external terminal thereon. The first die is attached and wire-bonded to the first surface of the substrate. The encapsulant covers the first die. The second die electrically connects to the second surface of the substrate. The second die is larger than the first die.

Abstract: Methods for forming solder bumps on a semiconductor device are provided. In one embodiment, a substrate is provided having at least one contact pad formed thereon. A passivation layer is formed overlying the substrate, the passivation layer having at least one opening therein exposing a portion of the contact pad. A UBM (Under Bump Metallurgy) layer is formed overlying the passivation layer and the contact pad. A patterned and etched light sensitive layer is provided overlying the UBM layer, the light sensitive layer defining at least one opening therein. A sidewall bump layer is formed over the exposed surfaces of the light sensitive layer and the UBM layer. A portion of the sidewall bump layer above the light sensitive layer is removed. A solder material is deposited in the opening bordered by the etched sidewall bump layer to form a solder column. The solder column is then reflown to create a solder bump.

Abstract: A heat spreader and package structure utilizing the same. The heat spreader is embedded in an encapsulant of a package and above a chip therein, wherein the package has a substrate, having a molding gate, and the chip has a center and a corner which is the farthest from the molding gate. The spreader includes a base with a hollow portion therethrough, a plurality of support leads, protruding from the base, on the inner edge, and a cap plate, having a hole at least directly above a region between the center and the corner of the chip, fixed by the support leads to be above the hollow portion, the cap plate.

Abstract: A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated by forming a recess in a substrate, such as a multi-layer substrate formed of organic dielectric materials. A ceramic layer is then affixed to the substrate in the recess. A die may be attached to the ceramic layer and the substrate may be attached to a printed circuit board.

Abstract: A method of protecting a bond pad during die-sawing comprising the following steps. A substrate having a bond pad formed thereover is provided. A bond pad protection layer is formed over the bond pad. The substrate is die-sawed and the bond pad protection layer is removed by heating.

Abstract: A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.

Abstract: A probe card having a member for sending and receiving electrical signals for operational testing of a semiconductor integrated circuit, and a plurality of probe pins extending from the member in a manner which causes free ends of the pins to contact wafer test pads substantially across a maximum dimension of the pads. Also, a test pad for a wafer or a substrate having a pad of electrically conductive material disposed in an area between seal rings of the wafer or substrate, the pad having a shape and/or a rotational orientation within the area between the seal rings that minimizes pad material immediately adjacent the seal rings.

Abstract: A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated by forming a recess in a substrate, such as a multi-layer substrate formed of organic dielectric materials. A ceramic layer is then affixed to the substrate in the recess. A die may be attached to the ceramic layer and the substrate may be attached to a printed circuit board.

Abstract: Disclosed herein is a bonding pad formed on an IC chip for electrically coupling the IC chip to another device or component, and associated methods of manufacturing the bonding pad. In one embodiment, the bonding pad comprises a bonding portion having a bonding surface configured to receive an electrical connector. The bonding pad further comprises a probing portion having a probing surface adjacent and electrically coupled to the bonding surface, and configured to receive a probe tip for testing to the operation of the integrated circuit chip. In this embodiment, the bonding pad comprises a first planar dimension measured across the bonding portion and the adjacent probing portion, where the bonding portion further comprises a second planar dimension measured substantially perpendicular to the first planar dimension, and the probing portion comprises a third planar dimension measured substantially perpendicular to the first planar dimension and being less than the second planar dimension.

Abstract: A substrate of semiconductor package for flip chip package is provided. The substrate comprises a plurality of bump pads; a solder mask layer covering a portion of the plurality of bump pads; and a plurality of dummy anchor plugs coupled beneath the bump pads.