Abstract: A substrate of semiconductor package for flip chip package is provided. The substrate comprises a plurality of bump pads; a solder mask layer covering a portion of the plurality of bump pads; and a plurality of dummy anchor plugs coupled beneath the bump pads.

Abstract: A stacked semiconductor device, and method of making, having a plurality of semiconductor chips of desired sizes stacked as one package, a first semiconductor chip is mounted on a first substrate. Solder balls are connected to contacts on the upper surface of the first substrate and a non-conductive layer is provided overlaying the first substrate and the first semiconductor chip. The solder balls are secured in cavities formed in the layer and extend beyond the top surface of the layer. A second semiconductor chip mounted on a second substrate is stacked on the layer with contacts on the lower surface of the second substrate in electrical contact with the extended portion of the solder balls, thereby connecting the second semiconductor chip with the first semiconductor chip.

Abstract: A 3D package has: a three-dimensional (3D) package substrate, a land grid array (LGA) or quad flat no-lead (QFN) package mounted on the 3D package substrate, the LGA or QFN package having an LGA or QFN die on a first side of an LGA or QFN package substrate, and a second die mounted directly on a second side of the LGA or QFN package substrate opposite the first side.

Abstract: Disclosed is a method of manufacturing a semiconductor package device. In one embodiment, the method includes providing a package substrate having a first coefficient of thermal expansion and at least one bonding pad on the substrate. The method also includes forming an integrated circuit chip having electrical devices, having at least one coupling structure for electrically coupling the chip to the at least one bonding pad, and having a second coefficient of thermal expansion different than the first coefficient of thermal expansion. The method further includes removing a portion of a thickness of the chip that is free of the electrical devices sufficient to allow the chip to distort substantially with the substrate during temperature changes despite the mismatch in their respective coefficients of thermal expansion. The method also includes bonding the chip to the substrate using the at least one coupling structure and the at least one bonding pad.

Abstract: A method of making a microelectronic assembly buying restraining a substrate in a fixture at room temperature, placing a flip chip on the substrate so that conductive bumps on the flip chip are aligned with contact pads on the substrate, heating the flip chip, the substrate and the fixture to reflow the conductive bumps on the flip chip, cooling the flip chip, substrate and fixture to solidify the conductive bumps and to mount the flip chip to the substrate, depositing an underfill between the flip chip and the substrate, curing the underfill by heating the flip chip, substrate, underfill and fixture to an elevated temperature, and removing the flip chip mounted substrate from the fixture.

Abstract: A packaging method and structures are disclosed. A first die is mounted on a package substrate. A chip scale package is mounted on the first die. The chip scale package comprises a chip scale package substrate and a second die mounted on a first surface of the chip scale package substrate. A third die is mounted on a second surface of the chip scale package substrate. Accordingly, the height of the stacked package can be reduced.

Abstract: A method of protecting a bond pad during die-sawing comprising the following steps. A substrate having a bond pad formed thereover is provided. A bond pad protection layer is formed over the bond pad. The substrate is die-sawed and the bond pad protection layer is removed by heating.

Abstract: A new method is provided for the interconnection of flip chips to a supporting substrate. The invention starts with a conventional first substrate, that serves as a semiconductor device support structure, over the surface of which a first pattern of contacts points has been provided. The invention then uses a second substrate, for instance a glass or quartz plate, and creates over the surface thereof a second pattern of solder bumps separated by solder non-wettable surfaces. The second pattern is a mirror image of the first pattern. By then overlying the first pattern of contact points with the second pattern of solder bumps, a step of reflow can be applied to the solder bumps, transferring the solder bumps from the second substrate to the contact points provided over the first substrate.

Abstract: The invention includes a method of wafer level chip scale packaging including providing a semiconductor device having a silicon based substrate with discrete devices defined therein and a contact pad near an upper surface thereof, a passivation layer overlying the silicon based substrate and the contact pad, and the passivation layer having an opening therein exposing at least a portion of the contact pad, and a redistribution trace electrically connected to the contact pad near a first end and having a second end of spaced a distance from the contact pad. Forming an encapsulation layer over the semiconductor device including the redistribution trace. Forming an opening in the encapsulation layer down to the redistribution trace. Forming a contact post in the opening in the encapsulation layer, and the contact post having a first end electrically connected to the redistribution trace and a second exposed end.

Abstract: A new method is provided for the interface between a stress relieve interface layer of polyimide and a thereover created layer of mold compound. The invention provides for creating a pattern in the stress relieve layer of polyimide before the layer of mold compound is formed over the stress relieve layer of polyimide.

Abstract: A new method is provided for the interface between a stress relieve interface layer of polyimide and a thereover created layer of mold compound. The invention provides for creating a pattern in the stress relieve layer of polyimide before the layer of mold compound is formed over the stress relieve layer of polyimide.

Abstract: Low stress concentration solder bumps are created on a semiconductor wafer by the removal of metal oxides on the edges of under bump metallurgy, (UBM). The removal of the oxides from the circular edge of the UBM allow the solder of the solder bump to wet the sides of the UBM, mainly the plated copper portion, thereby resulting in a solder bump structure with a filled undercut. This results in a lower stress concentration solder bump structure. This solder bump structure is obtained after the solder bumps have been reflowed on the wafer.

Abstract: A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area As is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation As=S1×S2, where S2 is the width of the second scribe line.

Abstract: A microelectronic assembly, and method of making the same, including a wire stitch bonded on an electroplated gold bump or electroless nickel/gold bump on a bond pad of an integrated circuit chip. The electroplated gold bump or electroless nickel/gold bump provides a relatively flat upper surface which is excellent for making a wire stitch bond thereto. The microelectronic assembly may include a multiple integrated circuit chip stack attached to a substrate such as a ball grid array. The electroplated gold bumps or electroless nickel/gold bumps may be formed on all of the integrated circuit chips and wire stitch bonds formed on the electroplated gold bumps or electroless nickel/gold bumps thereby connecting the integrated circuit chips to each other or to an underlying ball grid array.

Abstract: A method for protecting a passivation layer during a solder bump formation process including providing a semiconductor process wafer having a process surface including at least two metal layers comprising an uppermost metal layer and a lowermost metal layer said lowermost metal layer overlying a passivation layer including metal bonding pad regions; photolithographically patterning and anisotropically etching through a first thickness portion of at least the uppermost metal layer to form a first patterned metal layer portion disposed over the metal bonding pad regions and reveal a second thickness portion including the lowermost metal layer; forming a solder bump over the first patterned metal layer portion according to at least a first reflow process; and, anisotropically etching through the second thickness portion surrounding the completely formed solder bump to reveal the passivation layer.

Abstract: Low stress concentration solder bumps are created on a semiconductor wafer by the removal of metal oxides of under bump metallurgy, (UBM). The removal of the oxides from the circular edge of the UBM allow the solder of the solder bump to wet the sides of the UBM, mainly the plated portion, thereby resulting in a solder bump structure with a filled undercut. This results in a lower stress concentration solder bump structure. This solder bump structure is obtained after the solder bumps have been reflowed on the wafer.

Abstract: An under bump metallurgy (UBM) structure is described. Two UBM mask processes are utilized. First, a top layer of copper (Cu) and/or a middle layer of nickel-vanadium (NiV) or chrome-copper (CrCu) is personalized by standard photoprocessing and etching steps utilizing a bump based size mask. This is followed by patterning an underlying seed layer with a second, larger mask, thereby preventing damage to the aluminum cap and seed layer undercut during the etching process.

Abstract: A method including providing a first substrate having a first bond pad and a second bond pad; forming a subassembly comprising securing a second substrate to the first substrate with a ground layer interposed between the first substrate and the second substrate; forming a first trench in the subassembly through the first substrate so that the trench is defined at least in part by a side wall of the first substrate and through at least a portion of the ground layer; and forming a first electrically conductive layer overlying the first bond pad, the side wall of the first substrate and overlying a portion of the ground layer.

Abstract: A method for protecting a passivation layer during a solder bump formation process including providing a semiconductor process wafer having a process surface including at least two metal layers comprising an uppermost metal layer and a lowermost metal layer said lowermost metal layer overlying a passivation layer including metal bonding pad regions; photolithographically patterning and anisotropically etching through a first thickness portion of at least the uppermost metal layer to form a first patterned metal layer portion disposed over the metal bonding pad regions and reveal a second thickness portion including the lowermost metal layer; forming a solder bump over the first patterned metal layer portion according to at least a first reflow process; and, anisotropically etching through the second thickness portion surrounding the completely formed solder bump to reveal the passivation layer.

Abstract: An under bump metallurgy (UBM) structure is described. Two UBM mask processes are utilized. First, a top layer of copper (Cu) and/or a middle layer of nickel-vanadium (NiV) or chrome-copper (CrCu) is personalized by standard photoprocessing and etching steps utilizing a bump based size mask. This is followed by patterning an underlying seed layer with a second, larger mask, thereby preventing damage to the aluminum cap and seed layer undercut during the etching process.