Abstract: A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 ?m.

Abstract: Package structures and methods for forming the package structures are provided. A package structure includes a molding compound having a surface. The package structure also includes an integrated circuit die in the molding compound. The integrated circuit die has a portion protruding from the surface. The package structure further includes a planarization layer covering the surface. The planarization layer surrounds the portion of the integrated circuit die. In addition, the package structure includes a redistribution layer electrically connected to the integrated circuit die. The redistribution layer covers the planarization layer and the integrated circuit die.

Abstract: A package structure is provided. The package structure includes a first under bump metallurgy (UBM) layer formed over a first substrate, a first protrusion structure formed over the first UBM layer, wherein the first protrusion structure extends upward away from the first UBM layer. The package structure includes a first electrical connector formed over the first protrusion structure. The first electrical connector is surrounded by the first protrusion structure, and the first protrusion structure has an outer sidewall surface, and the outer sidewall surface of the first protrusion structure is aligned with an outer surface of the first UBM layer.

Abstract: Packaging method and wafer structures are described. A semiconductor wafer having dies, scribe streets surrounding the dies and between the dies and test pads in the scribe streets is provided. Wafer testing is performed to the semiconductor wafer through the test pads. A laser grooving process is performed to the semiconductor wafer along the scribe streets and the test pads in the scribe streets are removed to form laser scanned regions in the scribe streets. A mechanical dicing process is performed cutting through the semiconductor wafer along the scribe streets to singulate the dies. The singulated dies are packaged.

Abstract: A method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor chip comprising an active surface; forming a conductive bump over the active surface of the semiconductor chip; and coupling the conductive bump to a substrate. The conductive bump includes a plurality of bump segments including a first group of bump segments and a second group of bump segments. Each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip. A ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8.

Abstract: A package structure is provided. The package structure includes a dielectric layer formed over a first substrate and a conductive layer formed in the dielectric layer. The package structure includes an under bump metallurgy (UBM) layer formed over the dielectric layer, and the UBM layer is electrically connected to the conductive layer. The package structure also includes a first protrusion structure formed over the UBM layer, and the first protrusion structure extends upward away from the UBM layer. The package structure further includes a second protrusion structure formed over the UBM layer, and the second protrusion structure extends upward away from the UBM layer. The package structure includes a first conductive connector formed over the first protrusion structure; and a second conductive connector formed over the second protrusion structure. An air gap is formed between the first protrusion structure and the second protrusion structure.

Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

Abstract: Package structures and methods for forming the package structures are provided. A package structure includes a molding compound having a surface. The package structure also includes an integrated circuit die in the molding compound. The integrated circuit die has a portion protruding from the surface. The package structure further includes a planarization layer covering the surface. The planarization layer surrounds the portion of the integrated circuit die. In addition, the package structure includes a redistribution layer electrically connected to the integrated circuit die. The redistribution layer covers the planarization layer and the integrated circuit die.

Abstract: According to an exemplary embodiment, a method of detecting edge cracks in a die under test is provided. The method includes the following operations: receiving a command signal; providing power from the command signal; providing a response signal based on the command signal; and self-destructing based on the command signal.

Abstract: A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

Abstract: An embodiment device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a functional circuit region and a first portion of a seal ring spaced apart from the functional circuit region by a buffer zone. The device also includes a passivation layer over the interconnect structure and a second portion of the seal ring over the passivation layer and connected the first portion of the seal ring. The second portion of the seal ring is disposed in the buffer zone.

Abstract: A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.

Abstract: An embodiment device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a functional circuit region and a first portion of a seal ring spaced apart from the functional circuit region by a buffer zone. The device also includes a passivation layer over the interconnect structure and a second portion of the seal ring over the passivation layer and connected the first portion of the seal ring. The second portion of the seal ring is disposed in the buffer zone.

Abstract: According to an exemplary embodiment, a method of detecting edge cracks in a die under test is provided. The method includes the following operations: receiving a command signal; providing power from the command signal; providing a response signal based on the command signal; and self-destructing based on the command signal.

Abstract: According to an exemplary embodiment, a method of detecting edge cracks in a die under test is provided. The method includes the following operations: receiving a command signal; providing power from the command signal; providing a response signal based on the command signal; and self-destructing based on the command signal.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a semiconductor chip; a substrate facing an active surface of the semiconductor chip; and a conductive bump extending from the active surface of the semiconductor chip toward the substrate, wherein the conductive bump comprises: a plurality of bump segments comprising a first group of bump segments and a second group of bump segments, wherein each bump segment comprises the same segment height in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment comprises a volume defined by the multiplication of the segment height with the average cross-sectional area of the bump segment; wherein the ratio of the total volume of the first group of bump segments to the total volume of the second group of bump segments is between about 0.03 and about 0.8.

Abstract: According to an exemplary embodiment, a method of detecting edge cracks in a die under test is provided. The method includes the following operations: receiving a command signal; providing power from the command signal; providing a response signal based on the command signal; and self-destructing based on the command signal.

Abstract: Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress.

Abstract: A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.