Patents by Inventor Pei-Hsuan Lee
Pei-Hsuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220328309Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Publication number: 20220301944Abstract: A high atomic number material is applied to one or more surfaces of a semiconductor structure of a wafer. The one or more surfaces are at a depth different from a depth of a surface of the wafer. An electron beam is scanned over the semiconductor structure to cause a backscattered electron signal to be collected at a collector. A profile scan of the semiconductor structure is generated based on an intensity of the backscattered electron signal, at the collector, resulting from the high atomic number material. The high atomic number material increases the intensity of the backscattered electron signal for the one or more surfaces of the semiconductor structure such that contrast in the profile scan is increased. The increased contrast of the profile scan enables accurate critical dimension measurements of the semiconductor structure.Type: ApplicationFiled: March 19, 2021Publication date: September 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Pei-Hsuan LEE, Hung-Ming CHEN, Kuang-Shing CHEN, Yu-Hsiang CHENG, Xiaomeng CHEN
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Publication number: 20220293528Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.Type: ApplicationFiled: April 28, 2021Publication date: September 15, 2022Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
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Publication number: 20220293505Abstract: A package structure includes a carrier substrate, a die, and a first redistribution structure. The carrier substrate has a first surface and a second surface opposite to the first surface. The carrier substrate includes an insulating body and through carrier vias (TCV) embedded in the insulating body. The die is disposed over the firs surface of the carrier substrate. The die is electrically connected to the TCVs. The first redistribution structure is disposed on the second surface of the carrier substrate.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Yueh Wu, Chien-Ling Hwang, Jen-Chun Liao, Ching-Hua Hsieh, Pei-Hsuan Lee, Chia-Hung Liu
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Patent number: 11444002Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.Type: GrantFiled: July 29, 2020Date of Patent: September 13, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
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Patent number: 11380542Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: GrantFiled: September 4, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Patent number: 11282810Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.Type: GrantFiled: July 8, 2020Date of Patent: March 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Albert Wan, Ching-Hua Hsieh, Chung-Hao Tsai, Chuei-Tang Wang, Chao-Wen Shih, Han-Ping Pu, Chien-Ling Hwang, Pei-Hsuan Lee, Tzu-Chun Tang, Yu-Ting Chiu, Jui-Chang Kuo
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Publication number: 20220037228Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.Type: ApplicationFiled: July 29, 2020Publication date: February 3, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
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Publication number: 20210351491Abstract: A method of manufacturing an electronic device includes providing a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer, and removing at least a portion of each of the two conductive layers to respectively form an antenna pattern and a circuit pattern of a chip package at the two opposite surfaces of the core dielectric layer.Type: ApplicationFiled: July 22, 2021Publication date: November 11, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Hsuan Lee, Ching-Hua Hsieh, Chien-Ling Hwang, Yu-Ting Chiu, Jui-Chang Kuo
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Patent number: 11152258Abstract: A method of forming a semiconductor device includes patterning a dielectric layer to form a groove and depositing a plurality of conductive layers over the dielectric layer and in the groove. The first conductive layer is a liner layer, the second conductive layer is a metal film, and the third conductive layer is a capping layer. The first conductive layer is treated with a hydrogen plasma treatment to remove impurities. The first conductive layer is also treated with a hydrogen soak treatment to remove microvoids. The third conductive layer is treated with an ammonia plasma treatment to remove impurities. The third conductive layer is also treated with a hydrogen plasma treatment to remove additional impurities. The third conductive layer is also treated with a hydrogen soak treatment to remove microvoids.Type: GrantFiled: September 17, 2019Date of Patent: October 19, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Hsuan Lee, Chih-Chien Chi, Yu-Ying Liu
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Publication number: 20210304397Abstract: The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.Type: ApplicationFiled: June 11, 2021Publication date: September 30, 2021Inventors: PEI-HSUAN LEE, CHIEN-HSIANG HUANG, KUANG-SHING CHEN, KUAN-HSIN CHEN, CHUN-CHIEH CHIN
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Patent number: 11121046Abstract: A method includes: coupling a first end of a first conductive trace to a free electron source; scanning exposed surfaces of the first and a second conductive traces with an electron beam, the first conductive trace and a second conductive trace being alternately arranged and spaced apart; obtaining an image of the first conductive trace and the second conductive trace while performing the scanning; and determining a routing characteristic of the first conductive trace and the second conductive trace based on the image.Type: GrantFiled: January 16, 2019Date of Patent: September 14, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Pei-Hsuan Lee, Yu-Hsuan Huang, Chia-Chia Kan
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Publication number: 20210275675Abstract: The present invention relates to a modified starch and a method for obtaining the modified starch by using a debranching enzyme, such as isoamylase, pullulanase, limit dextrinase and the like. The debranching enzyme modified starch of present invention exhibits excellent film-forming capacity, film strength, and gelation ability, so as to be used as a material for making hard capsules without the use of coagulants and plasticizers.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Inventors: Ruei-Jan CHANG, Hsin-Yi CHAO, Pei-Hsuan LEE, Wei-Yu CHEN
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Publication number: 20210265228Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.Type: ApplicationFiled: May 10, 2021Publication date: August 26, 2021Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
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Publication number: 20210257293Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.Type: ApplicationFiled: October 14, 2020Publication date: August 19, 2021Inventors: Hui Lee, Po-Hsiang Huang, Wen-Sheh Huang, Jen Hung Wang, Su-Jen Sung, Chih-Chien Chi, Pei-Hsuan Lee
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Patent number: 11075439Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, a core dielectric layer disposed on the chip package, and an antenna pattern disposed on the core dielectric layer opposite to the chip package. The chip package includes a semiconductor chip, an insulating encapsulation encapsulating the semiconductor chip, and a redistribution structure electrically coupled to the semiconductor chip. The redistribution structure includes a first circuit pattern located at an outermost side of the chip package, and a patterned dielectric layer disposed between the first circuit pattern and the insulating encapsulation. The core dielectric layer is in contact with the first circuit pattern. The core dielectric layer and the patterned dielectric layer are of different materials. The antenna pattern is electrically coupled to the chip package.Type: GrantFiled: April 10, 2019Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei-Hsuan Lee, Ching-Hua Hsieh, Chien-Ling Hwang, Yu-Ting Chiu, Jui-Chang Kuo
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Patent number: 11037289Abstract: The present disclosure provides a method and a system for scanning wafer. The system captures a defect image of a wafer, and generates a reference image corresponding to the first defect image based on a reference image generation model. The system generates a defect marked image based on the defect image and the reference image.Type: GrantFiled: February 26, 2019Date of Patent: June 15, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Pei-Hsuan Lee, Chien-Hsiang Huang, Kuang-Shing Chen, Kuan-Hsin Chen, Chun-Chieh Chin
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Patent number: 11004758Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.Type: GrantFiled: June 17, 2019Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
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Publication number: 20210082752Abstract: A method of forming a semiconductor device includes patterning a dielectric layer to form a groove and depositing a plurality of conductive layers over the dielectric layer and in the groove. The first conductive layer is a liner layer, the second conductive layer is a metal film, and the third conductive layer is a capping layer. The first conductive layer is treated with a hydrogen plasma treatment to remove impurities. The first conductive layer is also treated with a hydrogen soak treatment to remove microvoids. The third conductive layer is treated with an ammonia plasma treatment to remove impurities. The third conductive layer is also treated with a hydrogen plasma treatment to remove additional impurities. The third conductive layer is also treated with a hydrogen soak treatment to remove microvoids.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Inventors: Pei-Hsuan Lee, Chih-Chien Chi, Yu-Ying Liu
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Patent number: 10879135Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.Type: GrantFiled: December 16, 2019Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shang-Wei Fang, Jing-Sen Wang, Yuan-Yao Chang, Wei-Ray Lin, Ting-Hua Hsieh, Pei-Hsuan Lee, Yu-Hsuan Huang