Patents by Inventor Pei-Lun Wang

Pei-Lun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210309732
    Abstract: Disclosed herein are anti-GM-CSF antibodies capable of binding to human GM-CSF and blocking its biological activities. Also provided herein are pharmaceutical compositions comprising the anti-GM-CSF antibodies and therapeutic and diagnostic uses of such antibodies.
    Type: Application
    Filed: March 10, 2021
    Publication date: October 7, 2021
    Applicant: ELIXIRON IMMUNOTHERAPEUTICS (HONG KONG) LIMITED
    Inventors: Cheng-Lun KU, Yu-Fang LO, Han-Po SHIH, Jing-Ya DING, Pei-Han CHUNG, Yin-Ping WANG
  • Patent number: 11121037
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Wei Tsai, Yu-Xuan Huang, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao, Jung-Hung Chang, Lo-Heng Chang, Pei-Hsun Wang, Kuo-Cheng Chiang
  • Patent number: 10964810
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.
    Type: Grant
    Filed: September 21, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Publication number: 20210074820
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a source region and a drain region within a substrate. A drift region is formed within the substrate such that the drift region is disposed laterally between the source region and the drain region. A first gate structure is formed over the drift region. An inter-level dielectric (ILD) layer is formed over the first gate structure. The ILD layers is patterned to define a field plate opening. A first field plate layer, a second field plate layer, and a third field plate layer are formed within the field plate opening.
    Type: Application
    Filed: November 19, 2020
    Publication date: March 11, 2021
    Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
  • Patent number: 10861946
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode. The field plate and first gate electrode respectively include metal materials.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
  • Publication number: 20200373395
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a field plate disposed over a drift region. A first gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an outer sidewall of the first gate electrode to the drain region. The etch stop layer overlies the drift region disposed between the source region and the drain region. A field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate overlies the drift region. A top surface of the field plate is aligned with a top surface of the first gate electrode and a bottom surface of the field plate is vertically above a bottom surface of the first gate electrode. The field plate and first gate electrode respectively include metal materials.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 26, 2020
    Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
  • Patent number: 10756208
    Abstract: The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a gate structure disposed over a substrate between source and drain regions and a dielectric layer laterally extending from over the gate structure to between the gate structure and the drain region. A composite etch stop layer having a plurality of different dielectric materials is stacked over the dielectric layer. A contact etch stop layer directly contacts an upper surface and sidewalls of the composite etch stop layer. A field plate is laterally surrounded by a first inter-level dielectric (ILD) layer and vertically extends from a top of the first ILD layer, through the contact etch stop layer, and into the composite etch stop layer.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong
  • Patent number: 10636904
    Abstract: The present disclosure, in some embodiments, relates to a transistor device having a field plate. The transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers are arranged over the gate electrode, and a field plate is arranged over the one or more dielectric layers. The field plate extends from a first outermost sidewall that is directly over an upper surface of the gate electrode to a second outermost sidewall that is between the gate electrode and the drain region and that extends to below the upper surface of the gate electrode.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Publication number: 20200020803
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a gate structure over a substrate and between a source region and a drain region. A composite etch stop structure is formed over the gate structure and a first inter-level dielectric (ILD) layer is formed over the composite etch stop structure. The composite etch stop structure has a plurality of stacked dielectric materials. The first ILD layer is etched to concurrently define contact openings extending to the substrate and a field plate opening extending to the composite etch stop structure. The contact openings and the field plate opening are concurrently filled with one or more conductive materials.
    Type: Application
    Filed: September 21, 2019
    Publication date: January 16, 2020
    Inventors: Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong
  • Publication number: 20200020802
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a source region and a drain region within a substrate. A gate structure is formed over the substrate and between the source region and the drain region. One or more dielectric layers are formed over the gate structure, and a first inter-level dielectric (ILD) layer is formed over the one or more dielectric layers. The first ILD layer laterally surrounds the gate structure. The first ILD layer is etched to define contact openings and a field plate opening. The contact openings and the field plate opening are filled with a conductive material.
    Type: Application
    Filed: September 21, 2019
    Publication date: January 16, 2020
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Publication number: 20190334032
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a gate structure disposed over a substrate between a source region and a drain region. A first inter-level dielectric (ILD) layer is disposed over the substrate and the gate structure and a second ILD layer is disposed over the first ILD layer. A field plate etch stop structure is between the first ILD layer and the second ILD layer. A field plate extends from an uppermost surface of the second ILD layer to the field plate etch stop structure. A plurality of conductive contacts extend from the uppermost surface of the second ILD layer to the source region and the drain region.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 31, 2019
    Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
  • Patent number: 10319719
    Abstract: A semiconductor device includes a first a first transistor configured to operate at a first threshold voltage level. The first transistor includes a first gate structure and a first drain terminal electrically coupled to the first gate structure. The semiconductor device also includes a second transistor configured to operate at a second threshold voltage level different from the first threshold voltage level. The second transistor includes a second source terminal and a second gate structure electrically coupled to the first gate structure. The first gate structure and the second gate structure comprise a first component in common, and the second gate structure further includes at least one extra component disposed over the first component. The number of the at least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chen-Yi Lee, Shih-Fen Huang, Pei-Lun Wang, Dah-Chuen Ho, Yu-Chang Jong, Mohammad Al-Shyoukh, Alexander Kalnitsky
  • Patent number: 10276839
    Abstract: A rechargeable battery includes a battery body and a connector plug. The battery body has a recess, a circuit board and a cell. The circuit board is electrically connected to the battery cell. The connector plug is pivotally connected to the battery body and electrically connected to the circuit board. The connector plug is foldable to be received in the recess. Accordingly, the connector plug is pivotally connected to the battery body and is foldable to be received in the recess, so the battery body can be charged by means of the connector plug connected to an external power supply, thereby improving convenience in using the rechargeable battery.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: April 30, 2019
    Inventors: Pei-Lun Wang, Xinping Luo
  • Publication number: 20190088777
    Abstract: The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a gate structure disposed over a substrate between source and drain regions and a dielectric layer laterally extending from over the gate structure to between the gate structure and the drain region. A composite etch stop layer having a plurality of different dielectric materials is stacked over the dielectric layer. A contact etch stop layer directly contacts an upper surface and sidewalls of the composite etch stop layer. A field plate is laterally surrounded by a first inter-level dielectric (ILD) layer and vertically extends from a top of the first ILD layer, through the contact etch stop layer, and into the composite etch stop layer.
    Type: Application
    Filed: October 30, 2018
    Publication date: March 21, 2019
    Inventors: Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong
  • Patent number: 10050371
    Abstract: A composite connection socket includes a metal housing, an insulative main body, a first row conductive terminal and a second row conductive terminal. The metal housing includes an accommodating space formed therein, and the insulative main body is received inside the accommodating space. The insulative main body includes a first side plate, a second side plate and a base; the first side plate and the second side plate are arranged corresponding to each other and protrude from the base. The first row conductive terminal is arranged on the first side plate and complies with a micro USB communication protocol interface. The second row conductive terminal is arranged on the second side plate and complies with a lightning standard interface. The composite connection socket is able to commonly accommodate two cable connectors of different standards of a micro USB connector or a lightning connector inserted therein.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 14, 2018
    Inventors: Pei-Lun Wang, Xinping Luo
  • Publication number: 20180219093
    Abstract: The present disclosure, in some embodiments, relates to a transistor device having a field plate. The transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers are arranged over the gate electrode, and a field plate is arranged over the one or more dielectric layers. The field plate extends from a first outermost sidewall that is directly over an upper surface of the gate electrode to a second outermost sidewall that is between the gate electrode and the drain region and that extends to below the upper surface of the gate electrode.
    Type: Application
    Filed: March 21, 2018
    Publication date: August 2, 2018
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Patent number: 9954100
    Abstract: A method includes forming a gate spacer along sidewalls of a gate structure, forming a source region and a drain region on opposite sides of the gate structure, wherein a sidewall of the source region is vertically aligned with a first sidewall of the gate spacer, depositing a dielectric layer over the substrate, depositing a conductive layer over the dielectric layer, patterning the dielectric layer and the conductive layer to form a field plate, wherein the dielectric layer comprises a horizontal portion extending from the second drain/source region to a second sidewall of the gate spacer and a vertical portion formed along the second sidewall of the gate spacer, forming a plurality of metal silicide layers by applying a salicide process to the conductive layer, the gate structure, the first drain/source region and the second drain/source region and forming contact plugs over the plurality of metal silicide layers.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chyi Liu, Pei-Lun Wang, Yuan-Tai Tseng, Yu-Hsing Chang, Shih-Chang Liu
  • Patent number: 9954097
    Abstract: The present disclosure relates to a transistor device having a field plate, and a method of formation. In some embodiments, the transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers laterally extend from over the gate electrode to a location between the gate electrode and the drain region. A field plate is located within an inter-level dielectric (ILD) layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the location and vertically extends from the one or more dielectric layers to a top surface of the ILD layer. A conductive contact is arranged over the drain region and is surrounded by the ILD layer. The conductive contact extends to the top surface of the ILD layer.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: April 24, 2018
    Assignee: Taiwan Seminconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
  • Patent number: 9923321
    Abstract: A composite connection socket includes a metal housing, an insulative main body, a first row conductive terminal and a second row conductive terminal. The metal housing includes an accommodating space formed therein, and the insulative main body is received inside the accommodating space. The insulative main body includes a first side plate, a second side plate and a base; the first side plate and the second side plate are arranged corresponding to each other and protrude from the base. The first row conductive terminal is arranged on the first side plate and complies with a micro USB communication protocol interface. The second row conductive terminal is arranged on the second side plate and complies with a lightning standard interface. The composite connection socket is able to commonly accommodate two cable connectors of different standards of a micro USB connector or a lightning connector inserted therein.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 20, 2018
    Inventors: Pei-Lun Wang, Xinping Luo
  • Patent number: D826171
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: August 21, 2018
    Inventors: Pei-Lun Wang, Xinping Luo