Patents by Inventor Pei Yu Wang

Pei Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11031481
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Chia-Hao Chang, Chih-Hao Wang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang
  • Publication number: 20210147034
    Abstract: A harmonic drive system for a pedal-electric-cycle comprises a transmission gear device including a wave generator assembled by an elliptical cam and a flexible bearing, a flexible-flexspline, a rigid-circular-spline having rigid-circular-spline internal gear teeth, a gear set, and a one-way clutch having an inner surface defining a space for containing a spindle of the pedal-electric-cycle. A first end of the flexible-flexspline has flexible-flexspline external gear teeth for meshing with the rigid-circular-spline internal gear teeth and an inner surface defining a space for containing the wave generator. The gear set has a first input portion connected to a second end of the flexible-flexspline, a second input portion having an inner surface defining a space for containing the one-way clutch, and an output portion connected to a sprocket of the pedal-electric-cycle. The first input portion has a first-input rotational axis. The second input portion has a second-input rotational axis.
    Type: Application
    Filed: August 4, 2020
    Publication date: May 20, 2021
    Inventors: Pei Yu WANG, Wei Sheng KE
  • Patent number: 11004232
    Abstract: An object detection apparatus includes a boundary box decision circuit and a processing circuit. The boundary box decision circuit receives lens configuration information of a lens, and refers to the lens configuration information to determine a bounding box distribution of bounding boxes that are assigned to different detection distances with respect to the lens for detection of a target object. The processing circuit receives a captured image that is derived from an output of an image capture device using the lens, and performs object detection upon the captured image according to the bounding box distribution of the bounding boxes.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: May 11, 2021
    Assignee: MEDIATEK INC.
    Inventors: Chih-Wei Chen, Pei-Kuei Tsung, Shao-Yi Wang, Hung-Jen Chen, Kuan-Yu Chen, Cheng-Lung Jen
  • Publication number: 20210122301
    Abstract: A vehicle decorative plate and a forming method thereof are disclosed. The vehicle decorative plate can be made into a vehicle emblem, a vehicle grille, a vehicle front bumper trim, a vehicle door trim or a vehicle rear bumper trim. The vehicle decorative plate includes a curved substrate, a display layer, and a curved covering. After the curved substrate is coated with a plating layer, unnecessary parts of the plating layer are removed by laser engraving to process the plating layer into the display layer. The curved covering is attached to the curved substrate and covers the display layer. At least one of the curved substrate and the curved covering is transparent or semi-transparent.
    Type: Application
    Filed: August 27, 2020
    Publication date: April 29, 2021
    Inventors: YI-KUAN LIN, PEI-YU WANG, FU-CHIEH HU
  • Patent number: 10964816
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Chieh Yang, Li-Yang Chuang, Pei-Yu Wang, Wei Ju Lee, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20210091179
    Abstract: A semiconductor device includes a substrate, semiconductor wires disposed over the substrate, a gate structure wrapping around each of the semiconductor wires, and an epitaxial source/drain (S/D) feature in contact with the semiconductor wires. A portion of the epitaxial S/D feature is horizontally surrounded by an air gap.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Inventors: Pei-Yu Wang, Wei Ju Lee
  • Publication number: 20210082803
    Abstract: Semiconductor devices and method of forming the same are disclosed herein. A semiconductor device according to the present disclosure includes a first dielectric layer having a first top surface and a contact via extending through the first dielectric layer and rising above the first top surface of the first dielectric layer.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Pei-Yu Wang, Cheng-Ting Chung, Wei Ju Lee
  • Publication number: 20210066469
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.
    Type: Application
    Filed: June 8, 2020
    Publication date: March 4, 2021
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20200388692
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Chun-Hsiung LIN, Chia-Hao CHANG, Chih-Hao WANG, Wai-Yi LIEN, Chih-Chao CHOU, Pei-Yu WANG
  • Patent number: 10756196
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Chia-Hao Chang, Chih-Hao Wang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang
  • Patent number: 10756197
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Chia-Hao Chang, Chih-Hao Wang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang
  • Publication number: 20200243408
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 30, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tsung-Yu LIN, Pei-Yu WANG, Chung-Wei HSU
  • Patent number: 10658255
    Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 19, 2020
    Assignee: ADVANCED SEMSCONDUCTOR ENGINEERING, INC.
    Inventors: Tsung-Yu Lin, Pei-Yu Wang, Chung-Wei Hsu
  • Publication number: 20200135923
    Abstract: A method for forming a semiconductor arrangement comprises forming a fin over a semiconductor layer. A gate structure is formed over a first portion of the fin. A second portion of the fin adjacent to the first portion of the fin and a portion of the semiconductor layer below the second portion of the fin are removed to define a recess. A stress-inducing material is formed in the recess. A first semiconductor material is formed in the recess over the stress-inducing material. The first semiconductor material is different than the stress-inducing material.
    Type: Application
    Filed: September 20, 2019
    Publication date: April 30, 2020
    Inventors: Pei-Yu WANG, Sai-Hooi Yeong
  • Publication number: 20200105930
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.
    Type: Application
    Filed: June 14, 2019
    Publication date: April 2, 2020
    Inventors: Kai-Chieh Yang, Li-Yang Chuang, Pei-Yu Wang, Wei Ju Lee, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20200035805
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 30, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung LIN, Chia-Hao CHANG, Chih-Hao WANG, Wai-Yi LIEN, Chih-Chao CHOU, Pei-Yu WANG
  • Publication number: 20200027960
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Chun-Hsiung LIN, Chia-Hao CHANG, Chih-Hao WANG, Wai-Yi LIEN, Chih-Chao CHOU, Pei-Yu WANG
  • Publication number: 20200006075
    Abstract: A method includes providing a structure having a substrate, first and second semiconductor fins extending from the substrate, and a dielectric fin between the first and second semiconductor fins; forming a temporary gate on top and sidewalls of the first and second semiconductor fins and the dielectric fin; forming gate spacers on sidewalls of the temporary gate; removing the temporary gate and a first portion of the dielectric fin between the gate spacers; forming a gate between the gate spacers and on top and sidewalls of the first and second semiconductor fins, wherein the dielectric fin is in physical contact with sidewalls of the gate; removing a second portion of the dielectric fin, thereby exposing the sidewalls of the gate; and performing an etching process to the gate through the exposed sidewalls of the gate, thereby separating the gate into a first gate segment and a second gate segment.
    Type: Application
    Filed: March 27, 2019
    Publication date: January 2, 2020
    Inventors: Pei-Yu Wang, Zhi-Chang Lin, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10510860
    Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Lin, Chia-Hao Chang, Chih-Hao Wang, Wai-Yi Lien, Chih-Chao Chou, Pei-Yu Wang
  • Patent number: D901380
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 10, 2020
    Assignees: GOLDEN TSANN YUH ENTERPRISE CO., LTD., PEPIDEA CO., LTD.
    Inventors: Yi-Ling Tsai, Pei-Yu Wang, Pai-Feng Chen